SM5849F Datasheet, PDF (22/26 Pages) Nippon Precision Circuits Inc – Asynchronous Sample Rate Converter

SM5849AF
TIMING DIAGRAMS
Input Timing Examples (DI, BCKI, LRCI)
Audio data input timing (right-justified 16-bit word, IFM1 = L, IFM2 = L, IWL1 = L, IWL2 = L)
LRCI(fsi)
1
BCKI(48fsi)
DI
24 25
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Audio data input timing (right-justified 24-bit word, IFM1 = L, IFM2 = L, IWL1 = H, IWL2 = H)
LRCI(fsi)
1
BCKI(48fsi)
24 25
48
MSB
LSBMSB
LSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Audio data input timing (left-justified 20-bit word, IFM1 = H, IFM2 = L, IWL1 = H, IWL2 = L)
LRCI(fsi)
1
BCKI(48fsi)
24 25
48
MSB
LSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
All data bits after the LSB (20th bit) are ignored. Note that more than 20 BCKI cycles are required.
Audio data input timing (IIS-format 24-bit word, IFM1 = H, IFM2 = H, IWL1 = L, IWL2 = H)
LRCI(fsi)
1
BCKI(64fsi)
32 33
64
MSB
LSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Audio data input timing (right-justified 24-bit word, LSB first,
IFM1 = H, IFM2 = H, IWL1 = L, IWL2 = H)
LRCI(fsi)
1
BCKI(64fsi)
DI
32 33
LSB
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
64
LSB
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NIPPON PRECISION CIRCUITS—22