SM5849F Datasheet, PDF (19/26 Pages) Nippon Precision Circuits Inc – Asynchronous Sample Rate Converter

SM5849AF
Internal Operating Status (STATE)
Internally, all functions are performed on 24-bit
serial data, and the conversion rate and filter type are
selected accordingly. The output format is 24-bit
left-justified.
Table 9. Status data description
Output bit position
1 to 20
21
22
23
24
Content
(Output data cycle/input data cycle) − 129
Ex.
1st
20th
00.111111111111011111 ⇒ 1.0 times
01.111111111111011111 ⇒ 2.0 times (1/2 conversion rate ratio)
00.011111111111011111 ⇒ 0.5 times (2.0 conversion rate ratio)
Not used.
Selected filter type
DA2
DA2
DA1
DA0 Filter type Conversion frequency (example)
0
0
0
1
Up converter
0
0
1
2
48 to 44.1kHz
DA1
0
1
0
3
44.1 to 32kHz
0
1
1
4
48 to 32kHz
1
0
0
5
96 to 48kHz, 48 to 24kHz
DA0
1
0
1
6
96 to 44.1kHz, 48 to 22.05kHz
Note that when THRUN is LOW, LRCO and BCKO
are not guaranteed to be synchronized to the STATE
output.
Input System Clock (ICLK, ICKSL)
The input system clock can be set to run at either
256fsi or 384fsi, where fsi is the input frequency on
LRCI.
Note that ICLK and LRCI should be divided from a
common clock source or PLL to maintain synchro-
nism.
Output System Clock (OCLK, OCKSL)
The output system clock can be set to run at either
256fso or 384fso, where fso is the output frequency
on LRCO. In through mode, OCLK and OCKSL
have no function and are not used.
Note that even in slave mode, a suitable clock must
be input on OCLK. A malfunction prevention circuit
uses this clock so that operation continues when the
ICLK stops.
Table 10. ICKSL and input system clock
ICKSL
HIGH
LOW
ICLK system clock rate
384fsi
256fsi
Table 11. SLAVE, OCKSL and output system clock
SLAVE
LOW
HIGH
OCKSL
HIGH
LOW
×
OCLK system clock rate
384fso
256fso
Not used
NIPPON PRECISION CIRCUITS—19