SM5849F Datasheet, PDF (15/26 Pages) Nippon Precision Circuits Inc – Asynchronous Sample Rate Converter

SM5849AF
Microcontroller Interface (MCOM, MDT, MCK, MLEN)
When MCOM is HIGH, the microcontroller inter-
face is active, comprising MDT (data), MCK (clock)
and MLEN (latch enable clock) interface pins.
Input data on MDT is synchronized to the MCK
clock. Data is read into the input stage shift register
on the rising edge of MCK. Accordingly, the input
data should change on the falling edge of MCK.
Input data enters an internal SIPO (serial-to-parallel
converter register), and then the parallel data is
latched into the mode register on the rising edge of
the latch enable clock MLEN.
The mode register addressed is determined by bit D1
of the 12 data bits before MLEN goes HIGH. If this
bit is LOW, then the data is read into the attenuation
data register as shown in figure 1. If this bit is HIGH,
then the data is read into the mode flag register as
shown in figure 2. The function of each bit in the
mode flag register is described in table 3.
MLEN
MMCD_,,,,,,KT _{,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,}
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D1212^{,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,}
MSB
LSB
"L"
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
Figure 1. Attenuation data format (D1 = LOW)
MLEN
MMCDKT^{,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,}
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
12
D12
,,,,,,,,,,,,,,,,,,,,,,,,
"H"
"L"
"L"
"L"
"L" FTST1 FTST2 FRATE F12DB FFSI1 FFSI2 FDEEM
Figure 2. Mode flag data format (D1 = HIGH)
NIPPON PRECISION CIRCUITS—15