SM5816AF_06 Datasheet, PDF (4/27 Pages) Nippon Precision Circuits Inc – 6-channel DSD-PCM Converter

SM5816AF
No.
Name
I/O
Property¹
Output
current
Input
voltage
Description
71
SELRAM
I
PD
–
3.3/5
FIR coefficient ROM/RAM select
L: ROM, H: RAM
72
SELFIR1
I
PD
–
3.3/5 FIR coefficient (ROM) select
73
SELFIR2
I
PD
SELFIR (2, 1) (L, L)
(L, H)
(H, L)
(H, H)
–
3.3/5
FIR coeff coeff 1 coeff 2 coeff 3 coeff 4
74
XMTPCM
I
PD
–
3.3/5
PCM output mute control input
L: mute-ON, H: mute-OFF
75
XMTDSD
I
PD
–
3.3/5
DSD output mute control input
L: mute-ON, H: mute-OFF
76
SEL8FS^{2, 3}
I
PD
–
3.3/5
PCM output rate select
L: 2fs, H: 8fs
77
SELEXT^{2, 3}
I
PD
78
SYNC ⁴
I
S
–
3.3/5
2fs output/external data output select
L: 2fs data, H: external data (EXID1, EXID2)
–
3.3/5 Forced sync control. Sync on rising edge
79
INIT^{4, 5}
I
S
–
3.3/5
Initialization control.
Active-LOW. Resync on “L” → “H”
80
VSS7
–
–
–
–
Ground pin 7
1. S = Schmitt, PD = pull-down resistor
2. The SEL8FS setting takes precedence over the SELEXT setting. In other words, 8fs PCM output is selected when SEL8FS is HIGH, and the SELEXT
settings are not effective. The SELEXT also selects relevant clock pins (F2LRCK, F2BCK, CKOUT).
3. Outputs not selected by SEL8FS and SELEXT are treated as described below:
• Data signals are tied LOW.
• When I/O pins F8WCK, F8BCK, F2LRCK, F2WCK are set as outputs, they function as outputs.
When they are set as inputs, they are ignored in input mode.
4. The output data is synchronized each time by event-driven operation despite the clock input/output. The resynchronization operation occurs to avoid
reading DSD input data at the falling edge of DSBCKF.
5. The internal flip-flops are all initialized in response to an active level on INIT, and outputs are tied HIGH or LOW during INIT active level input.
SEIKO NPC CORPORATION —4