SM5816AF_06 Datasheet, PDF (15/27 Pages) Nippon Precision Circuits Inc – 6-channel DSD-PCM Converter

SM5816AF
Clock Input/Output Selection and Synchronization Operation
DSD clock input/output switching
The DSD input bit clock (DSBCKF) and DSD output bit clock (DSBCKB) are switched using DIRDSCK1, 2
as shown in the following table.
DIRDSCK1
L
L
H
H
Setting
DIRDSCK2
L
H
L
H
I/O state
DSBCKF
DSBCKB
IN (Slave)
OUT (Master)
IN (Slave)
IN (Slave)
OUT (Master)
OUT (Master)
OUT (Master)
IN (Slave)
Reference connection diagram
(1) DIRDSCK1, 2 = (L, L)
Front-end
device
DSBCKF
SM5816AF
DSBCKB
Back-end
device
(2) DIRDSCK1, 2 = (L, H)
Front-end
device
DSBCKF _SM5816AF
DSBCKB
Back-end
device
(3) DIRDSCK1, 2 = (H, L)
Front-end
device
DSBCKF _SM5816AF
DSBCKB
Back-end
device
(4) DIRDSCK1, 2 = (H, H)
Front-end
device
DSBCKF _SM5816AF
DSBCKB
Back-end
device
Note. In mode (1) and (4) in the diagram above, the input clocks are output as-is in through mode.
PCM clock input/output switching
The 8fs and 2fs word/bit input/output clocks can be switched using DIR8CK and DIR2CK.
Note when external data is selected using SEL8FS and SELEXT, F2LRCK and F2BCK become outputs
despite the state of DIR2CK, so care must be taken with external connections.
The I/O settings for the data output mode selected are shown in the following table.
Mode
2fs
EXT
8fs
Mode setting
SEL8FS
SELEXT
L
L
L
H
H
L or H
2fs clock I/O state
DIR2CK
F2LRCK
F2BCK
L
OUT (Master)
H
IN (Slave)
L
OUT (EXILRCK, EXIBCK)
H
OUT (EXILRCK, EXIBCK)
L
OUT (clock output)
H
IN (invalid)
1. When external data is output in 2fs mode, MCK stops and the 8fs clock output stays stopped.
8fs clock I/O state
DIR8CK
F8WCK
F8BCK
L
OUT (clock output)
H
IN (invalid)
L
OUT (clock output)¹
H
IN (invalid)
L
OUT (Master)
H
IN (Slave)
SEIKO NPC CORPORATION —15