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SM5816AF_06 Datasheet, PDF (3/27 Pages) Nippon Precision Circuits Inc – 6-channel DSD-PCM Converter
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SM5816AF
No.
Name
I/O
Property1
Output
current
Input
voltage
Description
35
F8FR
O
–
2mA
–
8fs PCM data output: front right-channel
36
F8FL
O
–
2mA
–
8fs PCM data output: front left-channel
37
SELDH2
I
PD
–
3.3/5 Output dither rounding ON/OFF and summing position select
38
SELDH1
I
PD
SELDH (2, 1) (L, L)
(L, H)
(H, L)
(H, H)
–
3.3/5
Dither
OFF
1LSB
2LSB
4LSB
39
DIR2CK
I
PD
2fs output F2BCK, F2LRCK input/output select
L: output (master mode), H: input (slave mode)
–
3.3/5
Note: In 2fs-PCM output, when external inputs (EXID1, EXID2) are
selected for output (SELEXT = “H”), the DIR2CK setting is inactive,
and EXILRCK and EXIBCK are output as-is on F2LRCK and
F2BCK, respectively.
40
VSS4
–
–
–
–
Ground pin 4
41
VDD4
–
–
–
–
Supply pin 4
42
FMT2FS
I
PD
2fs PCM format
–
3.3/5
L: MSB-first left-justified 32-bit, H: IIS 32-bit
Note: In 2fs IIS 32-bit format, there are 64 F2BCK clock cycles per
F2LRCK clock cycle.
43
F2BCK
I/O
S
6mA
3.3/5 2fs or external data BCK
44
F2LRCK
I/O
S
6mA
3.3/5 2fs or external data LRCK
45
F2SLR
O
–
2mA
–
2fs PCM data output: surround left/right-channel
46
F2CSWEX2
O
–
2mA
–
2fs PCM data output: center/subwoofer channel or external data 2 output
47
F2FLREX1
O
–
2mA
–
2fs PCM data output: front left/right-channel or external data 1 output
48
TEST1
I
PD, S
–
3.3/5 Test pin 1 (must be open or tie LOW for normal operation)
49
CKOUT
O
–
12mA
–
System clock output. Clock output selected by SELEXT.
50
VSS5
–
–
–
–
Ground pin 5
51
VDD5
–
–
–
–
Supply pin 5
52
MCK
I
–
–
3.3/5 Master clock input: 512fs (22.5792MHz, fs = 44.1kHz)
53
TEST2
I
PD
–
3.3/5 Test pin 2 (must be open or tie LOW for normal operation)
54
TEST3
I
PD
–
3.3/5 Test pin 3 (must be open or tie LOW for normal operation)
55
EXIBCK
I
S
–
3.3/5 External PCM data BCK input
56
EXILRCK
I
S
–
3.3/5 External PCM data LRCK input
57
EXID2
I
–
–
3.3/5 External PCM data input 2
58
EXID1
I
–
–
3.3/5 External PCM data input 1
59
EXIMCK
I
–
–
3.3/5 External system clock input
60
VSS6
–
–
–
–
Ground pin 6
61
VDD6
–
–
–
–
Supply pin 6
62
DSBCKF
I/O
S
6mA
3.3/5 DSD data input bit clock. Controlled by DIRDSCK1, 2
63
DSIFL
I
–
–
3.3/5 DSD data input: front left-channel
64
DSIFR
I
–
–
3.3/5 DSD data input: front right-channel
65
DSICT
I
–
–
3.3/5 DSD data input: center channel
66
DSISW
I
–
–
3.3/5 DSD data input: subwoofer channel
67
DSISL
I
–
–
3.3/5 DSD data input: surround left-channel
68
DSISR
I
–
–
3.3/5 DSD data input: surround right-channel
69
DIRDSCK1
I
PD
–
3.3/5
DSBCKF I/O select
L: input (slave), H: output (master)
70
DIRDSCK2
I
PD
–
3.3/5
DSBCKB I/O select
L: output (master), H: input (slave)
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