SM5816AF_06 Datasheet, PDF (2/27 Pages) Nippon Precision Circuits Inc – 6-channel DSD-PCM Converter

SM5816AF
PIN DESCRIPTION
No.
Name
I/O
Property¹
Output
current
1
VDD1
–
–
–
2
MSHIFT
I
S
–
3
MLATCH
I
S
–
4
MDATA
I
S
–
5
DSGAIN
I
PD
–
6
SELSBSW
I
PD
–
7
SELSBR
I
PD
–
8
SELMCU
I
PD
–
9
MONTOR
O
–
2mA
10
VSS1
–
–
–
11
DSBCKB
I/O
S
6mA
12
DSOSR
O
–
2mA
13
DSOSL
O
–
2mA
14
DSOSBR
O
–
2mA
15
DSOSBL
O
–
2mA
16
DSOSW
O
–
2mA
17
DSOCT
O
–
2mA
18
DSOFR
O
–
2mA
19
DSOFL
O
–
2mA
20
VSS2
–
–
–
21
VDD2
–
–
–
22
DIR8CK
I
PD
–
23
FMT8FS
I
PD
–
24
FMT8WCK
I
PD
–
25
F8BCK
I/O
S
6mA
26
F8WCK
I/O
S
6mA
27
F8SR
O
–
2mA
28
F8SL
O
–
2mA
29
F8SBR
O
–
2mA
30
VSS3
–
–
–
31
VDD3
–
–
–
32
F8SBL
O
–
2mA
33
F8SW
O
–
2mA
34
F8CT
O
–
2mA
Input
voltage
–
3.3/5
3.3/5
3.3/5
3.3/5
3.3/5
3.3/5
3.3/5
–
–
3.3/5
–
–
–
–
–
–
–
–
–
–
3.3/5
3.3/5
3.3/5
3.3/5
3.3/5
–
–
–
–
–
–
–
–
Description
Supply pin 1
Serial control: shift clock
Serial control: latch clock
Serial control: command data
DSD signal gain setting
L: 100% modulation = 0dB, H: 50% modulation = 0dB
DSD-SW input to SW/(SBL, SBR) output select
L: SW input to SW output, H: SW input to (SBL, SBR) output
Note. It effects both of DSD and 8fs outputs.
DSD 8fs-(SBL, SBR) output select
L: SBL output only, H: both SBL, SBR output
Note: Valid only when SELSBSW is HIGH.
Control method select
L: pin control, H: serial interface data control
Parameter change monitor output
Ground pin 1
DSD through-mode data output: bit clock, controlled by DIRDSCK1, 2
DSD through-mode data output: surround right-channel
DSD through-mode data output: surround left-channel
DSD through-mode data output: surround back right-channel
DSD through-mode data output: surround back left-channel
DSD through-mode data output: subwoofer channel
DSD through-mode data output: center channel
DSD through-mode data output: front right-channel
DSD through-mode data output: front left-channel
Ground pin 2
Supply pin 2
8fs output F8BCK, F8WCK input/output select
L: output (master mode), H: Input (slave mode)
8fs PCM format (MSB-first)
L: MSB-first left-justified 32-bit, H: MSB-first right-justified 24-bit
Note: In 8fs right-justified 24-bit format, there are a fixed 32 bit clock
(F8BCK) cycles per word clock (F8WCK) cycle.
Note: In 8fs right-justified 24-bit format, the upper empty bits are for sign
extension.
8fs PCMWCK format
L: “H” → “L” (rising-edge word boundary)
H: “L” → “H” (falling edge word boundary)
8fs PCM BCK (bit clock)
8fs PCM WCK (word clock)
8fs PCM data output: surround right-channel
8fs PCM data output: surround left-channel
8fs PCM data output: surround back right-channel
Ground pin 3
Supply pin 3
8fs PCM data output: surround back left-channel
8fs PCM data output: subwoofer channel
8fs PCM data output: center channel
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