SM5816AF_06 Datasheet, PDF (16/27 Pages) Nippon Precision Circuits Inc – 6-channel DSD-PCM Converter

SM5816AF
Input clock sync operation and resynchronization
The data output internal operation and interface processing occur as event driven operations using the word
clock word boundary as the event trigger, hence the output signals are always synchronized regardless of the
word clock and bit clock I/O state.
As regards DSD input, the data (BUF_A) on the rising edge of bit clock (DSBCKF) and data (BUF_B) one half
of the bit clock period later are selected and read in when the DSD output and PCM output event starts, to
avoid the transitions in the DSD input signal.
At this time, the sync operation that determines which data was read in, after the INIT and SYNC rising edge,
occurs when the word clock word boundary is detected after the first DSBCKF falling edge.
SNYC/INIT
DSI**
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
D (n)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;^{D (n+1)};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ^{D (n+2)} ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;^{D (n+3)};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ^{D (n+3)} ;;;;;;;;;;;;;;;;
DSBCKF
(BUF_A)
(BUF_B)
(IN_PHASE)
(DSD_SEL)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;^D;;;;;;;;;;;;;;^B;;;;;;;;;;;;;;^{(;;;;;;;;;;;;;;n;;;;;;;;;;;;;;(-S1;;;;;;;;;;;;;;e);;;;;;;;;;;;;;le;;;;;;;;;;;;;;ct;;;;;;;;;;;;;;D";;;;;;;;;;;;;;BA;;;;;;;;;;U(;;;;;;;Fn_;;;;;;;)B;;;;;;;";;;;;;;) D;;;;;;;B;;;;;;;;;;;(n};;;;⁾;;;;;;;;^D;;;;^A;;;;⁽;;;;ⁿ⁺¹⁾
DA (n+2)
DB (n+1)
Select "BUF_A"
DB (n+2)
DA (n+3)
DB (n+2)
DSBCKB
DSO**
(PCM_SEL)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;^D;;;;;;;^B;;;;;;;;;;;;;;⁽ⁿ;;;;;;;^-;;;;;;;₍²_S;;;;;;;⁾_e;;;;;;;_le;;;;;;;_ct;;;;;;;_";;;;;;;_B;;;;;;;_U;;;;;;;_{F_};;;;;;;_A;;;;;;;^D_";;;;;;;₎^B;;;;;;;⁽;;;;;;;ⁿ;;;;;;;^-1;;;;;;;⁾;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;^D;;;;;;;^B;;;;;;;⁽;;;;;;;ⁿ⁾;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DA (n+2)
DA (n+3)
F8WCK
/F2LRCK
(Filter Input) _{;;;;;;;;;;;;;;;}D_;;;A_;;;(_;;;n-_;;;1_;;;) _{;;;;;;;;;;;;;;;;;;;;;;;;;;;}D_;;;A_;;;(_;;;n_;;;) _{;;;;;;;;;;;;;;;;;;;;;}D_;;;A_;;;(n_;;;+_;;;1_;;;) _;;;;;;
(Word boundary edge)
DB (n+1)
DB (n+2)
DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins
DSO**: DSOFL, DSOFR, DSOSL, DSOSR, DSOCT, DSOSW, DSOSBL, DSOSBR pins
Figure 1. Input timing sync operation due to INIT, SYNC
1) After the SYNC/INIT rising edge is detected, the phase reference signal (IN_PHASE) for the input data
buffer selected is determined on the first DSBCKF falling edge.
2) Then, after the IN_PHASE transition, the subsequent data buffer is determined on the first DSBCKB edge
and F8WCK/F2LRCK word boundary edge.
(The input data buffer selection for DSD output and PCM output is independent.)
Synchronization adjustment due to INIT/SYNC edge may cause 1 DSD data bit to be lost or made redundant
due to input/output clock phase difference. If this would be problem, individual outputs should be muted for
the following intervals.
[DSD output] 4 DSBCKB (64fs) clock cycles
[8fs PCM output] 34 F8WCK (8fs) clock cycles
[2fs PCM output] 18 F2LRCK (2fs) clock cycles
SEIKO NPC CORPORATION —16