UPD70F3208 Datasheet, PDF (694/757 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 25 FLASH MEMORY
25.5.3 RESET pin
If the reset signal of the flash programmer is connected to the RESET pin that is connected to the reset signal
generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset
signal generator.
If the reset signal is input from the user system while the flash memory programming mode is set, the flash
memory will not be correctly programmed. Do not input any signal other than the reset signal of the flash
programmer.
Figure 25-11. Signal Collision (RESET Pin)
V850ES/KF1,
V850ES/KG1,
V850ES/KJ1
RESET
Signal collision
Flash programmer
connection signal
Reset signal generator
Output pin
In the flash memory programming mode, the signal output by the reset
signal generator collides with the signal output by the flash programmer.
Therefore, isolate the signal of the reset signal generator.
25.5.4 Port pins
When the flash memory programming mode is set, all the port pins, except those used for communication with the
flash programmer, go into an output high-impedance state. If this causes a problem in the external device connected
to a port due to prohibition of the output high-impedance state (etc.), connect the port to VDD or VSS via a resistor.
25.5.5 Other signal pins
Connect the X1, X2, XT1, XT2, and REGC pins in the same status as in the normal operation mode.
To input the operating clock from the programmer, however, connect the clock out of the programmer to X1, and its
inverse signal to X2.
25.5.6 Power supply
Supply power as follows.
VDD = EVDD
Supply the same power as in the normal operation mode to the other power supply pins (AVREF0, AVREF1, AVSS,
BVDD, and BVSS).
Caution VDD of the flash programmer has a power monitor function. Be sure to connect VDD and VSS to
VDD and GND of the flash programmer.
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User’s Manual U15862EJ3V0UD