UPD70F3208 Datasheet, PDF (548/757 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 18 I²C BUS
18.3 Configuration
I²Cn includes the following hardware.
Table 18-1. Configuration of I²Cn
Item
Configuration
Registers
IIC shift registers 0 and 1 (IIC0, IIC1)
Slave address registers 0 and 1 (SVA0, SVA1)
Control registers
IIC control registers 0 and 1 (IICC0, IICC1)
IIC status registers 0 and 1 (IICS0, IICS1)
IIC flag registers 0, 1 (IICCF0, IICCF1)
IIC clock selection registers 0 and 1 (IICCL0, IICCL1)
IIC function expansion registers 0 and 1 (IICX0, IICX1)
Remark n = 0 (V850ES/KF1, V850ES/KG1)
n = 0, 1 (V850ES/KJ1)
(1) IIC shift registers 0 and 1 (IIC0, IIC1)
IICn is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-bit serial data.
IICn can be used for both transmission and reception.
Write and read operations to IICn are used to control the actual transmit and receive operations.
IICn is set by an 8-bit memory manipulation instruction.
RESET input clears IIC0 and IIC1 to 00H.
(2) Slave address registers 0 and 1 (SVA0, SVA1)
SVAn sets local addresses when in slave mode.
SVAn is set by an 8-bit memory manipulation instruction.
RESET input clears SVA0 and SVA1 to 00H.
(3) SO latch
The SO latch is used to retain the SDAn pin’s output level.
(4) Wakeup controller
This circuit generates an interrupt request when the address received by this register matches the address
value set to slave address register n (SVAn) or when an extension code is received.
(5) Clock selector
This selects the sampling clock to be used.
(6) Serial clock counter
This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive
operations and is used to verify that 8-bit data was sent or received.
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User’s Manual U15862EJ3V0UD