UPD70F3208 Datasheet, PDF (502/757 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION
• 3-wire SOAn: Serial data output
SIAn: Serial data input
SCKAn: Serial clock I/O
• Transmission/reception completion interrupt: INTCSIAn
• Internal 32-byte buffer RAM
Remark n = 0 (V850ES/KF1)
n = 0, 1 (V850ES/KG1, V850ES/KJ1)
17.2 Configuration
CSIAn consists of the following hardware.
Table 17-1. Configuration of CSIAn
Item
Register
Control registers
Configuration
Serial I/O shift register An (SIOAn)
Automatic data transfer address count register n (ADTCn)
CSIAn buffer RAM (CSIAnBm, CSIAnBmL, CSIAnBmH) (m = 0 to F)
Serial operation mode specification register n (CSIMAn)
Serial status register n (CSISn)
Serial trigger register n (CSITn)
Divisor selection register n (BRGCAn)
Automatic data transfer address point specification register n (ADTPn)
Automatic data transfer interval specification register n (ADTIn)
502
User’s Manual U15862EJ3V0UD