UPD70F3208 Datasheet, PDF (546/757 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 18 I²C BUS
Figure 18-2. Block Diagram of I²Cn
SDAn
Noise
eliminator
Slave address
register n (SVAn)
Match
signal
IIC shift register n
(IICn)
Internal bus
IIC status register n
(IICSn)
IIC control register n
(IICCn)
MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn
IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn
SET
CLEAR
SO latch
DQ
CLn1,
CLn0
Start
condition
generator
N-ch open-
drain output
SCLn
Noise
eliminator
Data hold time
correction
circuit
ACK detector
Start condition
detector
Stop condition
detector
Serial clock counter
ACK output
circuit
Wakeup controller
Interrupt request
signal generator
INTIICn
N-ch open-
drain output
Serial clock controller
Serial clock wait
controller
fXX
Prescaler
Bus status
detector
CLDn DADn SMCn DFCn CLn1 CLn0
CLXn
STCFn IICBSYn STCENn IICRSVn
IIC clock selection
register n (IICCLn)
Internal bus
IIC function expansion
register n (IICXn)
IIC flag
register n (IICFn)
Remark n = 0 (V850ES/KF1, V850ES/KG1)
n = 0, 1 (V850ES/KJ1)
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User’s Manual U15862EJ3V0UD