UPD70F3208 Datasheet, PDF (379/757 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 9 8-BIT TIMERS H0 AND H1
9.4.2 PWM pulse generator mode operation
In the PWM mode, a pulse of any duty and cycle can be output.
8-bit timer H compare register n0 (CMPn0) controls the timer output (TOHn) cycle. Rewriting the CMPn0 register
during timer operation is prohibited.
8-bit timer H compare register n1 (CMPn1) controls the timer output (TOHn) duty. The CMPn1 register can be
rewritten during timer operation.
The operation in the PWM mode is as follows.
After timer counting starts, when the count value of 8-bit timer counter Hn and the value of the CMPn0 register
match, the TOHn output becomes active and 8-bit timer counter Hn is cleared to 00H. When the count value of 8-bit
timer counter Hn and the CMPn1 register match, TOHn output becomes inactive.
(1) Usage method
In the PWM mode, a pulse of any duty and cycle can be output.
<1> Set each register.
Figure 9-4. Register Settings in PWM Pulse Generator Mode
(i) 8-bit timer H mode register n (TMHMDn) settings
TMHEn CKSHn2 CKSHn1 CKSHn0 TMMDn1 TMMDn0 TOLEVn TOENn
TMHMDn
0
0/1
0/1
0/1
1
0
0/1
1
(ii) CMPn0 register setting
• Compare value (N): Sets cycle
(ii) CMPn1 register setting
• Compare value (N): Sets duty
Remarks 1. n = 0, 1
2. 00H ≤ CMPn1 (M) < CMPn0 (N) ≤ FFH
Enables timer output
Sets timer output level inversion
Selects PWM mode
Selects count clock (fCNT)
Stops count operation
<2> When TMHEn = 1 is set, counting starts.
User’s Manual U15862EJ3V0UD
379