UPD70F3208 Datasheet, PDF (334/757 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05
7.4.4 Operation as external event counter
Setting procedure
The basic operation setting procedure is as follows.
<1> Set the pins to the TI0n0 pin mode (see CHAPTER 4 PORT FUNCTIONS).
<2> Set the CRC0n register (see Figure 7-18 for the setting value).
<3> Set the count clock using the PRM0n register.
<4> Set any value (except for 0000H) to the CRC0n0 register.
<5> Enable the INTTM0n0 (or INTTM0n1) interrupt (see CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING
FUNCTION for details).
<6> Set the TMC0n register: Start operation (see Figure 7-18 for the setting value).
The external event counter counts the number of clock pulses input to the TI0n0 pin from an external source by
using 16-bit timer counter 0n (TM0n).
Each time the valid edge specified by prescaler mode register 0n (PRM0n) has been input, the TM0n register is
incremented.
When the count value of the TM0n register matches the value of 16-bit timer capture/compare register 0n0
(CR0n0), the TM0n register is cleared to 0 and an interrupt request signal (INTTM0n0) is generated.
Set the CR0n0 register to a value other than 0000H (one-pulse count operation is not possible).
The edge is specified by bits 4 and 5 (ESn00 and ESn01) of the PRM0n register. The rising, falling, or both the
rising and falling edges can be specified.
The valid edge is detected through sampling at a count clock cycle of fXX/4, and the capture operation is not
performed until the valid level is detected twice. As a result, noise with a short pulse width can be eliminated.
Cautions 1. When using the TM00 to TM03 registers as external event counters, the timer outputs (TO00
to TO03) cannot be used.
2. The value of the CR0n0 and CR0n1 registers cannot be changed during timer count
operation. However, the CR0n1 register value can be changed in the PPG output mode. For
details, refer to 7.4.2 PPG output operation.
Remark n = 0 to 5
334
User’s Manual U15862EJ3V0UD