UPD70F3208 Datasheet, PDF (488/757 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 16 CLOCKED SERIAL INTERFACE 0 (CSI0)
(2) Clock phase selection
The following shows the timing when changing the conditions for clock phase selection (CKPn bit of CSICn
register) and data phase selection (DAPn bit of CSICn register) under the following conditions.
• Data length = 8 bits (CCLn bit of CSIM0n register = 0)
• First bit of transfer data = MSB (DIRn bit of CSIM0n register = 0)
• No interrupt request signal delay control (CSITn bit of CSIM0n register = 0)
Figure 16-3. Timing Chart According to Clock Phase Selection (1/2)
(a) When CKPn bit = 0, DAPn bit = 0
SCK0n (I/O)
SI0n (input)
SO0n (output)
Reg_R/W
INTCSI0n interrupt
CSOTn bit
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
(b) When CKPn bit = 1, DAPn bit = 0
SCK0n (I/O)
SI0n (input)
SO0n (output)
Reg_R/W
INTCSI0n interrupt
CSOTn bit
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Remarks 1. n = 0, 1 (V850ES/KF1, V850ES/KG1), n = 0 to 2 (V850ES/KJ1)
2. Reg_R/W: Internal signal. This signal indicates that a clocked serial interface receive buffer
register n and nL (SIRBn/SIRBnL) read or clocked serial interface transmit buffer
register n and nL (SOTBn/SOTBnL) write was performed.
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User’s Manual U15862EJ3V0UD