UPD784031 Datasheet, PDF (67/90 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCONTROLLER

µPD784031
(2) IOE1, IOE2
Parameter
Serial clock cycle time
(SCK1, SCK2)
Symbol
tCYSK1
Input
Conditions
VDD = +5.0 V ± 10 %
Serial clock low-level width
(SCK1, SCK2)
tWSKL1
Output
Input
Internal, divided by 16
VDD = +5.0 V ± 10 %
Serial clock high-level width
(SCK1, SCK2)
tWSKH1
Output
Input
Internal, divided by 16
VDD = +5.0 V ± 10 %
Setup time for SI1 and SI2
(to SCK1, SCK2↑)
tSSSK1
Hold time for SI1 and SI2
(to SCK1, SCK2↑)
tHSSK1
Output delay time for SO1 and tDSOSK
SO2 (to SCK1, SCK2↓)
Output hold time for SO1 and tHSOSK
SO2 (to SCK1, SCK2↑)
Output Internal, divided by 16
When data is transferred
MIN.
250
500
T
85
210
0.5T - 40
85
210
0.5T - 40
40
40
0
0.5tCYSK1 - 40
Remarks 1. The values in this table are those when CL is 100 pF.
2. T: Serial clock cycle set by software. The minimum value is 16/fXX.
(3) UART, UART2
Parameter
ASCK clock input cycle time
Symbol
Conditions
tCYASK
VDD = +5.0 V ± 10 %
ASCK clock low-level width
tWASKL VDD = +5.0 V ± 10 %
ASCK clock high-level width tWASKH VDD = +5.0 V ± 10 %
MIN.
125
250
52.5
85
52.5
85
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
ns
ns
MAX.
Unit
ns
ns
ns
ns
ns
ns
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