UPD784031 Datasheet, PDF (63/90 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCONTROLLER

µPD784031
AC CHARACTERISTICS (TA = -40 to +85 °C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)
(1) Read/write operation (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time
tSAST
VDD = +5.0 V ± 10 %
(0.5 + a) T - 15
ns
(0.5 + a) T - 31
ns
ASTB high-level width
tWSTH
VDD = +5.0 V ± 10 %
(0.5 + a) T - 17
ns
(0.5 + a) T - 40
ns
Address hold time (to ASTB↓) tHSTLA VDD = +5.0 V ± 10 %
0.5T - 24
ns
0.5T - 34
ns
Address hold time (to RD↑) tHRA
0.5T - 14
ns
Delay from address to RD↓ tDAR
VDD = +5.0 V ± 10 %
(1 + a) T - 9
ns
(1 + a) T - 15
ns
Address float time (to RD↓) tFRA
0
ns
Delay from address to data input tDAID
VDD = +5.0 V ± 10 %
(2.5 + a + n) T - 37 ns
(2.5 + a + n) T - 52 ns
Delay from ASTB↓ to data input tDSTID
VDD = +5.0 V ± 10 %
(2 + n) T - 40
ns
(2 + n) T - 60
ns
Delay from RD↓ to data input tDRID
VDD = +5.0 V ± 10 %
(1.5 + n) T - 50 ns
(1.5 + n) T - 70 ns
Delay from ASTB↓ to RD↓
tDSTR
0.5T - 9
ns
Data hold time (to RD↑)
tHRID
0
ns
Delay from RD↑ to address active tDRA
After program VDD = +5.0 V ± 10 %
0.5T - 8
ns
is read
0.5T - 12
ns
After data is VDD = +5.0 V ± 10 %
1.5T - 8
ns
read
1.5T - 12
ns
Delay from RD↑ to ASTB↑
tDRST
0.5T - 17
ns
RD low-level width
tWRL
VDD = +5.0 V ± 10 %
(1.5 + n) T - 30
ns
(1.5 + n) T - 40
ns
Address hold time (to WR↑) tHWA
0.5T - 14
ns
Delay from address to WR↓ tDAW
VDD = +5.0 V ± 10 %
(1 + a) T - 5
ns
(1 + a) T - 15
ns
Delay from ASTB↓ to data output tDSTOD VDD = +5.0 V ± 10 %
0.5T + 19
ns
0.5T + 35
ns
Delay from WR↓ to data output tDWOD
0.5T - 11
ns
Delay from ASTB↓ to WR↓
tDSTW
0.5T - 9
ns
Remarks T:
a:
n:
TCYK (system clock cycle time)
1 (during address wait), otherwise, 0
Number of wait states (n ≥ 0)
63