UPD78P324 Datasheet, PDF (64/80 Pages) NEC – 16-/8-Bit Single-Chip Microcomputers

µPD78P324, 78P324(A)
PROM Write Mode Timing
A0-A16
tAS
D0-D7 ^Hi-Z
VPP
VPP
VDDP
VDDP + 1.5
VDDP
VDDP
VIH
CE
VIL
tDS
tVPS
tVDS
tCES
VIH
PGM
VIL
VIH
OE
VIL
Program
Data input
tDH
Program verify
tDF
Hi-Z _{Data output}
Hi-Z
tAH
tPW
tOES
tOE
Cautions
1. Ensure to apply VDDP before VPP, and disconnect it after VPP.
2. Ensure that VPP does not exceed +13.5 V even when the overshoot is included.
3. Taking out or putting in while +12.5 V is applied to VPP may cause adverse effects on the reliability.
PROM Read Mode Timing
A0-A16
Vailed address
CE
OE
D0-D7
tACC ^{Note 1}
Hi-Z
tOE ^{Note 1}
tOH
Data output
tDF ^{Note 2}
Hi-Z
Notes 1. To read within the range of tACC, please make sure that the delay time from CE’s falling edge of the
OE input is up to tACC-tOE.
2. tDF refers to the time when either OE or CE became VIH first.
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