UPD78P324 Datasheet, PDF (40/80 Pages) NEC – 16-/8-Bit Single-Chip Microcomputers

µPD78P324, 78P324(A)
(2) µPD78P324(A) Electrical Specifications (9/9)
AC Timing Test Point
VDD
0V
0.8VDD or 2.2V
0.8V
Test point
0.8VDD or 2.2V
0.8V
A/D Converter Characteristics (TA = –40 to +85 °C, VDD = +5 V ±10 %, VSS = AVSS = 0 V, VDD –0.5 V ≤ AVDD ≤ VDD)
Parameter
Resolution
Total error^{Note 1}
Quantization error
Conversion time
Sampling time
Zero-scale error^{Note 1}
Full-scale error^{Note 1}
Non-linear error^{Note 1}
Analog input voltage^{Note 2}
Analog input impedance
Reference voltage
AVREF current
AVDD supply current
A/D converter data retention current
Symbol
Condition
4.5 V ≤ AVREF ≤ AVDD
3.5 V ≤ AVREF ≤ AVDD
MIN.
10
tCONV
144
tSAMP
24
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF ≤ AVDD
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF ≤ AVDD
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF ≤ AVDD
VIAN
0
When not sampled
RAN
When sampled
AVREF
3.4
AIREF
AIDD
Operation mode
AIDDDR
AVDDDR = 2.5 V
STOP mode
AVDDDR=5 V±10%
TYP.
MAX.
±0.4
±0.7
±1/2
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
10
Note 3
1.0
2.0
2
10
±2.5
±4.5
±2.5
±4.5
±2.5
±4.5
AVDD
AVDD
3.0
6.0
15
50
Unit
bit
%FSR
%FSR
LSB
tCYK
tCYK
LSB
LSB
LSB
LSB
LSB
LSB
V
MΩ
V
mA
mA
µA
µA
Notes 1. Quantization error excluded.
2. When VIAN = 0 V, the conversion result becomes 000H.
When 0 V < VIAN < AVREF, the conversion is performed at a resolution of 10 bits.
When AVREF ≤ VIAN ≤ AVDD, the conversion result is 3FFH.
3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram
below. (The values in the diagram are TYP. values; therefore, they are not assured.)
Analog input pin
20kΩ
30pF
( input
capacitance
included )
10pF
40