UPD17010 Datasheet, PDF (291/424 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE DEDICATED TO DIGITAL TUNING SYSTEM

µPD17010
19.11 Using Serial Interface 0
19.11.1 Using I²C bus mode
The I²C bus mode is selected by resetting the SIO0CH flag to “0” and setting the SB flag to “1”.
In this mode, the P0A3/SDA and P0A2/SCL pins are used.
Figure 19-14 shows the I/O block and communication method in the I²C bus mode.
Table 19-6 shows the pins used in the I²C bus mode and the function and operation of the control register.
As shown in Figure 19-14 and Table 19-6, a master or slave operation can be performed in the I²C bus mode. Data
can be transmitted (TX) or received (RX) during master and slave operations.
The master or slave operation is selected by the SIO0MS flag, and the reception or transmission is selected by
the SIO0TX flag.
During the master operation, the internal shift clock is output from the P0A2/SCL pin. If transmission is carried
out at this time, data is output from the P0A3/SDA pin at the falling edge of the shift clock. During reception, the status
of the P0A3/SDA pin is input to the presettable shift register 0 at the rising edge of the shift clock.
During master or slave operation, the start and stop conditions of serial communication can be detected by the
SBSTT and SBBSY flags.
The start and stop conditions are usually output by the master. This output is made by program (by controlling
each pin as a general-purpose output port pin).
During the slave operation, the P0A2/SCL pin is floated and the device waits for an external clock. If transmission
is performed at this time, data is output from the P0A3/SDA pin at the falling edge of the shift clock. If reception is
performed, the status of the P0A3/SDA pin is input to the presettable shift register 0 at the rising edge of the clock
applied to the P0A2/SCL pin.
During reception by the master or slave, an acknowledge signal is output each time 8-bit data has been
communicated.
During transmission by the master or slave, an acknowledge signal is detected each time 8-bit data has been
communicated.
The P0A3/SDA and P0A2/SCL pins are N-ch open-drain output pins; therefore, the communication line goes low
if either the master or slave outputs a low level.
When the values output to the P0A3/SDA and P0A2/SCL pins are read, the “status of pin at that time” is read.
Paragraphs (1) through (4) below Table 19-6 show program examples for transmission and reception during master
and slave operations.
291