UPD17010 Datasheet, PDF (162/424 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE DEDICATED TO DIGITAL TUNING SYSTEM

µPD17010
13.3 CE Reset
CE reset is executed when the CE pin goes high.
When the CE pin goes high, the RESET signal is output in synchronization with the rising edge of the next basic
timer 0 carry FF setting pulse, and the device is reset.
When CE reset is executed, the program counter, stack, system registers, and some control registers are initialized
by the RESET signal, and the program is started from address 0000H.
For the values to which the program counter, stack, system registers, and control registers are to be initialized,
refer to the description of each register.
The operation of CE reset differs depending on whether the clock stop instruction is used or not.
This is described in details in 13.3.1 and 13.3.2 below.
13.3.3 describes points to be noted in executing CE reset.
13.3.1 CE reset when clock stop instruction (STOP s) is not used
Figure 13-2 shows the operation.
When the clock stop instruction (STOP s) is not used, the basic timer clock select register of the control registers
is not initialized.
Therefore, after the CE pin has gone high, the RESET signal is output at the rising edge of the basic timer 0 carry
FF setting pulse selected at that time (1 ms, 5 ms, 100 ms, or 250 ms), and reset is effected.
Figure 13-2. CE Reset Operation When Clock Stop Instruction Is Not Used
5V
VDD
0V
H
CE
L
H
XOUT
L
Basic timer 0 carry ^H
FF setting pulse _L
H
IRES
L
H
RES
L
H
RESET
L
Normal
operation
Normal
operation
CE reset is executed at the rising
edge of the basic timer 0
carry FF setting pulse
If basic timer 0 carry FF setting time selected at this time
is tSET, the relation between this period "t" and tSET is 0 < t <
tSET according to the rising timing of the CE pin. During this
period, the program continues operation.
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