UPD17010 Datasheet, PDF (191/424 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE DEDICATED TO DIGITAL TUNING SYSTEM

µPD17010
14.5 Phase Comparator (φ-DET), Charge Pump, and Unlock Detection Block
14.5.1 Configuration of phase comparator, charge pump, and unlock detection block
Figure 14-4 shows the configuration of the phase comparator, charge pump, and unlock detection block.
The phase comparator compares the phase of the divided frequency “fN” output by the programmable divider with
that of the reference frequency “fr” output by the reference frequency generator, and outputs an up request signal (UP)
and down request signal (DW).
The charge pump outputs the signal output by the phase comparator from the error out pins (EO1 and EO0 pins).
The unlock detection block consists of a sensibility select circuit and an unlock FF, and detects the unlock status
of the PLL frequency synthesizer.
The following 14.5.2, 14.5.3, and 14.5.4 respectively describe the operations of the phase comparator, charge
pump, and unlock detection block.
Figure 14-4. Configuration of Phase Comparator, Charge Pump, and Unlock Detection Block
Phase comparator (φ -DET)
fr
Reference
frequency
generator
Control register
Address
15H
05H
Bit b3 b2 b1 b0 b3 b2 b1 b0
PPPP
P
LLLL
L
UUUU
L
Flag L
symbol S
L
S
L
S
L
S
0
0
0
U
L
EEEE
NNNN
3210
Unlock detection block
UP
Sensibility
select
Unlock FF
Program- _fN
mable
divider
Charge pump
DW
PLL disable signal
VDD
P-ch
EO1
N-ch
VDD
P-ch
EO0
N-ch
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