UPD17010 Datasheet, PDF (101/424 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE DEDICATED TO DIGITAL TUNING SYSTEM

µPD17010
11.3.4 Configuration and function of basic timer 0 carry flip-flop (FF) judge register (BTM0CYJG)
The basic timer 0 carry flip-flop (FF) judge register detects the status of the basic timer 0 carry flip-flop (FF) of the
internal timer.
The configuration and function of BTM0CYJG are illustrated below.
Name
Basic timer 0 carry
FF judge register
(BTM0CYJG)
Flag Symbol
b3 b2 b1 b0
B
T
M
0000
C
Y
Address
Read/
Write
17H R & Reset
Detects status of basic timer 0 carry FF
0 Basic timer 0 carry FF is not set
1 Basic timer 0 carry FF is set
Fixed to "0"
Power-ON
Clock stop
CE
0000
1
1
The BTM0CY flag is set at time intervals set by the basic timer clock select register (BTMCLK).
The status of this flag is detected by the “PEEK” instruction via the window register.
If the BTM0CY flag is set at this time, its value is transferred to the window register and then the BTM0CY flag
is reset (Read & Reset).
Because the BTM0CY flag is reset to “0” at power-ON reset and is set to “1” at CE reset and at CE reset after
execution of the clock stop instruction, it can be used to detect a power failure.
The BTM0CY flag is not set once VDD has been applied until the “PEEK” instruction is executed. Once the “PEEK”
instruction has been executed, it is set at time intervals set by the basic timer clock select register.
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