UPD17010 Datasheet, PDF (1/424 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE DEDICATED TO DIGITAL TUNING SYSTEM

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD17010
4-BIT SINGLE-CHIP MICROCONTROLLER
WITH HARDWARE DEDICATED TO DIGITAL TUNING SYSTEM
The µPD17010 is a 4-bit single-chip CMOS microcontroller containing hardware for digital tuning systems.
The CPU uses a 17K architecture and can directly manipulate the data memory and control various operations
and peripheral hardware with a single instruction. All instructions are 16-bit 1-word instructions.
As the peripheral hardware, a prescaler for digital tuning that operates at up to 150 MHz, PLL frequency
synthesizer, and frequency counter, as well as many I/O ports, LCD controller/driver, 12-bit timer, A/D converter,
D/A converter (PWM output), clock generator port are provided.
Therefore, a high-performance digital tuning system with sophisticated functions can be configured with a
single chip. The µPD17P010 is available as a one-time PROM model of the µPD17010. This one-time PROM
model can be used for evaluation of the program of the µPD17010 and small-scale production of the application
system.
FEATURES
• 17K architecture: General-purpose register
system
• Program memory (ROM)
16K bytes (7932 × 16 bits)
• General-purpose data memory (RAM)
432 × 4 bits
• Instruction execution time
4.44 µs (with 4.5-MHz crystal resonator)
• Decimal operation
• Table reference
• Hardware for PLL frequency synthesizer
Dual modulus prescaler (150 MHz MAX.),
programmable divider, phase comparator,
charge pump
• A variety of peripheral hardware
General-purpose I/O ports, LCD controller/driver,
serial interface, 12-bit timer, A/D converter, D/A
converter (PWM output), clock generator port,
frequency counter
• Many interrupts
External: 1
Internal: 4
External/internal (multiplexed): 1
• Power-ON reset, reset by CE pin, and power failure
detection circuit
• Low power-dissipation CMOS
• Supply voltage: 5 V±10 %
The information in this document is subject to change without notice.
Document No. U10340EJ2V0DS00 (2nd edition)
(Previous No. ID-2878)
Date Published October 1995 P
Printed in Japan
©
1991