UPD78F9177 Datasheet, PDF (25/56 Pages) NEC – 8-BIT SINGLE-CHIP MICROCONTROLLER

µPD78F9177, 78F9177Y
Mnemonic
Operand
Bytes Clock
Operation
Flags
Z AC CY
INCW
rp
1
4
rp ← rp + 1
DECW
rp
1
4
rp ← rp – 1
ROR
A, 1
1
2
(CY, A7 ← A0, Am-1 ← Am) × 1
×
ROL
A, 1
1
2
(CY, A0 ← A7, Am+1 ← Am) × 1
×
RORC
A, 1
1
2
(CY ← A0, A7 ← CY, Am-1 ← Am) × 1
×
ROLC
A, 1
1
2
(CY ← A7, A0 ← CY, Am+1 ← Am) × 1
×
SET1
saddr.bit
3
6
(saddr.bit) ← 1
sfr.bit
3
6
sfr.bit ← 1
A.bit
2
4
A.bit ← 1
PSW.bit
3
6
PSW.bit ← 1
×××
[HL].bit
2
10 (HL).bit ← 1
CLR1
saddr.bit
3
6
(saddr.bit) ← 0
sfr.bit
3
6
sfr.bit ← 0
A.bit
2
4
A.bit ← 0
PSW.bit
3
6
PSW.bit ← 0
×××
[HL].bit
2
10 (HL).bit ← 0
SET1
CY
1
2
CY ← 1
1
CLR1
CY
1
2
CY ← 0
0
NOT1
CY
1
2
CY ← CY
×
CALL
!addr16
3
6
(SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,
PC ← addr16, SP ←SP – 2
CALLT
[addr5]
1
8
(SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1)
PCL ← (00000000, addr5)
SP ← SP – 2
RET
1
6
PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RETI
1
8
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0
RRR
PUSH
PSW
1
2
(SP – 1) ← PSW, SP ← SP – 1
rp
1
4
(SP – 1) ← rpH, (SP – 2) ← rpL,
SP ← SP -– 2
POP
PSW
1
4
PSW ← (SP), SP ← SP + 1
RRR
rp
1
6
rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
MOVW
SP, AX
2
8
SP ← AX
AX, SP
2
6
AX ← SP
Remark One clock of an instruction is one clock of the CPU clock (fCPU) selected using the processor clock
control register (PCC).
Data Sheet U14022EJ1V0DS00
25