UPD78F9177 Datasheet, PDF (23/56 Pages) NEC – 8-BIT SINGLE-CHIP MICROCONTROLLER

µPD78F9177, 78F9177Y
Mnemonic
Operand
Bytes
XCHW
AX, rp^Note
1
ADD
A, #byte
2
saddr, #byte
3
A, r
2
A, saddr
2
A, !addr16
3
A, [HL]
1
A, [HL + byte]
2
ADDC
A, #byte
2
saddr, #byte
3
A, r
2
A, saddr
2
A, !addr16
3
A, [HL]
1
A, [HL + byte]
2
SUB
A, #byte
2
saddr, #byte
3
A, r
2
A, saddr
2
A, !addr16
3
A, [HL]
1
A, [HL + byte]
2
SUBC
A, #byte
2
saddr, #byte
3
A, r
2
A, saddr
2
A, !addr16
3
A, [HL]
1
A, [HL + byte]
2
Note Only when rp = BC, DE, HL
Clock
Operation
8
AX ←→ rp
4
A, CY ← A + byte
6
(saddr), CY ← (saddr) + byte
4
A, CY ← A + r
4
A, CY ← A + (saddr)
8
A, CY ← A + (addr16)
6
A, CY ← A + (HL)
6
A, CY ← A + (HL + byte)
4
A, CY ← A + byte + CY
6
(saddr), CY ← (saddr) + byte + CY
4
A, CY ← A + r + CY
4
A, CY ← A+ (saddr) + CY
8
A, CY ← A+ (addr16) +CY
6
A, CY ← A + (HL) + CY
6
A, CY ← A+ (HL + byte) + CY
4
A, CY ← A – byte
6
(saddr), CY ← (saddr) – byte
4
A, CY ← A – r
4
A, CY ← A – (saddr)
8
A, CY ← A – (addr16)
6
A, CY ← A – (HL)
6
A, CY ← A – (HL + byte)
4
A, CY ← A – byte – CY
6
(saddr), CY ← (saddr) – byte – CY
4
A, CY ← A – r – CY
4
A, CY ← A – (saddr) – CY
8
A, CY ← A – (addr16) – CY
6
A, CY ← A – (HL) – CY
6
A, CY ← A – (HL + byte) – CY
Flags
Z AC CY
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
×××
Remark One clock of an instruction is one clock of the CPU clock (fCPU) selected using the processor clock
control register (PCC).
Data Sheet U14022EJ1V0DS00
23