MC9S12DJ64 Datasheet, PDF (79/126 Pages) Motorola, Inc – MC9S12DJ64 Device User Guide V01.17

MC9S12DJ64 Device User Guide — V01.17
Table 22-1 Suggested External Component Values
Component
Purpose
Type
Value
C1
VDD1 filter cap
ceramic X7R
100 .. 220nF
C2
VDD2 filter cap
ceramic X7R
100 .. 220nF
C3
VDDA filter cap
ceramic X7R
100nF
C4
VDDR filter cap
X7R/tantalum
>=100nF
C5
VDDPLL filter cap
ceramic X7R
100nF
C6
VDDX filter cap
X7R/tantalum
>=100nF
C7
OSC load cap
C8
OSC load cap
C9 / C_S
C10 / C_P
PLL loop filter cap
PLL loop filter cap
See PLL specification chapter
C11 / C_DC
DC cutoff cap
Colpitts mode only, if recommended by
quartz manufacturer
R1
PLL loop filter res
See PLL specification chapter
R2 / R_B
R3 / R_S
PLL loop filter res
PLL loop filter res
Pierce mode only
Q1
Quartz
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
• Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins(C1 - C6).
• Central point of the ground star should be the VSSR pin.
• Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
• VSSPLL must be directly connected to VSSR.
• Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.
• Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
• Central power input should be fed in at the VDDA/VSSA pins.
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