MC9S12DJ64 Datasheet, PDF (65/126 Pages) Motorola, Inc – MC9S12DJ64 Device User Guide V01.17

MC9S12DJ64 Device User Guide — V01.17
Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the HCS12 Core and all peripheral
modules. Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide and OSC Block User Guide for details on clock generation.
Core Clock
HCS12 CORE
BDM CPU
MEBI MMC
INT BKP
EXTAL
OSC CRG ^{Bus Clock}
XTAL
Oscillator Clock
Flash
RAM
EEPROM
ECT
ATD0, 1
PWM
SCI0, SCI1
SPI0
CAN0
IIC
BDLC
PIM
Figure 3-1 Clock Connections
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