MC68EC030 Datasheet, PDF (6/36 Pages) Motorola, Inc – Second-Generation 32-Bit Enhanced Embedded Controller

Freescale Semiconductor, Inc.
31
16 15
31
16 15
0
A7'
(ISP)
0
A7"
(MSP)
INTERRUPT
STACK POINTER
MASTER
STACK POINTER
15
87
0
(CCR)
SR
STATUS
REGISTER
31
0
VBR
VECTOR
BASE REGISTER
31
20
SFC
ALTERNATE FUNCTION
CODE REGISTERS
DFC
31
0
CACR
CACHE CONTROL
REGISTER
31
0
CAAR
CACHE ADDRESS
REGISTER
31
0
AC0
ACCESS CONTROL
REGISTER 0
31
0
AC1
ACCESS CONTROL
REGISTER 1
15
0
ACUSR
ACU STATUS
REGISTER
Figure 4. Supervisor Programming Model Supplement
The status register (see Figure 5) contains the interrupt priority mask (three bits) as well as the following
condition codes: extend (X), negate (N), zero (Z), overflow (V), and carry (C). Additional control bits
indicate that the controller is in the trace mode (T1 or T0), supervisor/user state (S), and master/interrupt
state (M).
SYSTEM BYTE
USER BYTE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T1 T0 _{S M 0} I ₂ I1 I ₀ 0 0 0 X N Z V C
TRACE ENABLE
SUPERVISOR/USER STATE
MASTER/INTERRUPT STATE
INTERRUPT
PRIORITY MASK
CONDITION
CODES
EXTEND
NEGATIVE
ZERO
OVERFLOW
CARRY
Figure 5. Status Register
6
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