MC68EC030 Datasheet, PDF (27/36 Pages) Motorola, Inc – Second-Generation 32-Bit Enhanced Embedded Controller

Freescale Semiconductor, Inc.
NOTES:
1. This number can be reduced to 5 ns if strobes have equal loads.
2. If the asynchronous setup time (#47A) requirements are satisfied, the DSACKx low to data setup time
(#31) and DSACKx low to BERR low setup time (#48) can be ignored. The data must only satisfy the
data-in clock low setup time (#27) for the following clock cycle and BERR must only satisfy the late
BERR low to clock low setup time (#27A) for the following clock cycle.
3. This parameter specifies the maximum allowable skew between DSACK0 to DSACK1 asserted or
DSACK1 to DSACK0 asserted; specification #47A must be met by DSACK0 or DSACK1.
4. This specification applies to the first (DSACK0 or DSACK1) DSACKx signal asserted. In the absence of
DSACKx, BERR is an asynchronous input using the asynchronous input setup time (#47A).
5. DBEN may stay asserted on consecutive write cycles.
6. The minimum values must be met to guarantee proper operation. If this maximum value is exceeded,
BG may be reasserted.
7. This specification indicates the minimum high time for ECS and OCS in the event of an internal cache hit
followed immediately by another cache hit, a cache miss, or an operand cycle.
8. This specification guarantees operation with the MC68881/MC68882, which specifies a minimum time
for DS negated to AS asserted (specification #13A in the MC68881/MC68882 User's Manual).
Without this specification, incorrect interpretation of specifications #9A and #15 would indicate that
the MC68EC030 does not meet the MC68881/MC68882 requirements.
9. This specification allows a system designer to guarantee data hold times on the output side of data
buffers that have output enable signals generated with DBEN. The timing on DBEN precludes its use
for synchronous READ cycles with no wait states.
10. These specifications allow system designers to guarantee that an alternate bus master has stopped
driving the bus when the MC68EC030 regains control of the bus after an arbitration sequence.
11. DS will not be asserted for synchronous write cycles with no wait states.
12. These hold times are specified with respect to strobes (asynchronous) and with respect to the clock
(synchronous). The designer is free to use either time.
13. Synchronous inputs must meet specifications #60 and #61 with stable logic levels for all rising edges of
the clock while AS is asserted. These values are specified relative to the high level of the rising clock
edge. The values originally published were specified relative to the low level of the rising clock edge.
14. This specification allows system designers to qualify the CS signal of an MC68881/MC68882 with AS
(allowing 7 ns for a gate delay) and still meet the CS to DS setup time requirement (spec 8B of the
MC68881/MC68882 User's Manual).
MOTOROLA
F^Mor^CM⁶⁸o^Ere^C0In³⁰for^Tm^Ea^Ct^Hio^Nn^ICO^An^LTh^Dis^ATP^Aroduct,
27
Go to: www.freescale.com