MC68EC030 Datasheet, PDF (13/36 Pages) Motorola, Inc – Second-Generation 32-Bit Enhanced Embedded Controller

Freescale Semiconductor, Inc.
DATA CACHE
The organization of the data cache (see Figure 7) is similar to that of the instruction cache. However, the
tag is composed of the upper 24 address bits, the four valid bits, and all three function code bits, explicitly
specifying the address space associated with each line. The data cache employs a write-through policy
with programmable write allocation of data writes— i.e., if a cache hit occurs on a write cycle, both the data
cache and the external device are updated with the new data. If a write cycle generates a cache miss, the
external device is updated, and a new data cache entry can be replaced or allocated for that address,
depending on the state of the write-allocate (WA) bit in the CACR.
LONG-WORD
SELECT
TAG
INDEX
FFF A
CC C 3
21 0 1
AA AAAAAAAAAAAAAAAAAAAAAA
2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 ^{ACCESS ADDRESS}
32 1098765432109876543210
TAG
V VVV
1 OF 16
SELECT
TAG REPLACE
VALID
COMPARATOR
LINE HIT
ENTRY HIT
DATA FROM DATA
CACHE DATA BUS
DATA TO EXECUTION
UNIT
CACHE CONTROL LOGIC
CACHE SIZE = 64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE = 1
Figure 7. On-Chip Data Cache Organization
OPERAND TRANSFER MECHANISM
The MC68EC030 offers three different mechanisms by which data can be transferred into and out of the
chip. Asynchronous bus cycles, compatible with the asynchronous bus on the MC68020 and MC68030,
can transfer data in a minimum of three clock cycles; the amount of data transferred on each cycle is
determined by the dynamic bus sizing mechanism on a cycle-by-cycle basis with the data transfer and size
acknowledge (DSACKx) signals. Synchronous bus cycles, compatible with the synchronous bus on the
MC68030, are terminated with the synchronous termination (STERM) signal and always transfer 32-bits
of data in a minimum of two clock cycles, increasing the bus bandwidth available for other bus masters,
MOTOROLA
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