MC68EC030 Datasheet, PDF (3/36 Pages) Motorola, Inc – Second-Generation 32-Bit Enhanced Embedded Controller

Freescale Semiconductor, Inc.
information. The instruction pipe and other individual control sections provide the secondary decode of
instructions and generate the actual control signals that result in the decoding and interpretation of
nanoROM and microROM information.
The instruction and data cache blocks operate independently from the rest of the machine, storing
information read by the bus controller for future use with very fast access time. Each cache resides on its
own address bus and data bus, allowing simultaneous access to both. The data and instruction caches
are organized as a total of 64 long-word entries (256 bytes) with a line size of four long words. The data
cache uses a write-through policy with programmable write allocation for cache misses.
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