MC68EC030 Datasheet, PDF (22/36 Pages) Motorola, Inc – Second-Generation 32-Bit Enhanced Embedded Controller

Freescale Semiconductor, Inc.
DRIVE
TO 2.4 V
2.0 V
CLK
DRIVE TO
0.5 V
A
B
OUTPUTS(1) CLK
VALID ^{2.0 V}
OUTPUT n
0.8 V
OUTPUTS(2) CLK
2.0 V
0.8 V
0.8 V
2.0 V _VALID
OUTPUT n + 1
0.8 V
A
B
VALID ^{2.0 V}
OUTPUT n
0.8 V
2.0 V
0.8 V
VALID
OUTPUT n+1
INPUTS(3) CLK
DRIVE TO
2.4 V
DRIVE TO
0.5 V
INPUTS(4) CLK
C
D
2.0 V
VALID
2.0 V
0.8 V
INPUT
0.8 V
C
2.0 V
0.8 V
D
VALID
INPUT
2.0 V
0.8 V
ALL SIGNALS(5)
2.0 V
0.8 V
E
F
2.0 V
0.8 V
NOTES:
1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This output timing is applicable to all parameters specified relative to the falling edge of the clock.
3. This input timing is applicable to all parameters specified relative to the rising edge of the clock.
4. This input timing is applicable to all parameters specified relative to the falling edge of the clock.
5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal.
LEGEND:
A. Maximum output delay specification.
B. Minimum output hold time.
C. Minimum input setup time specification.
D. Minimum input hold time specification.
E. Signal valid to signal valid specification (maximum or minimum).
F. Signal valid to signal invalid specification (maximum or minimum).
DRIVE
TO 2.4 V
DRIVE
TO 0.5 V
Figure 9. Drive Levels and Test Points for AC Specifications
22
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