MC68EC030 Datasheet, PDF (18/36 Pages) Motorola, Inc – Second-Generation 32-Bit Enhanced Embedded Controller

Freescale Semiconductor, Inc.
Table 3. Signal Index
Signal Name
Function Codes
Address Bus
Data Bus
Size
Operand Cycle Start
External Cycle Start
Read/Write
Read-Modify-Write Cycle
Address Strobe
Data Strobe
Data Buffer Enable
Data Transfer and Size
Acknowledge
Synchronous
Termination
Cache Inhibit In
Cache Inhibit Out
Cache Burst Request
Cache Burst
Acknowledge
Interrupt Priority Level
Interrupt Pending
Autovector
Bus Request
Bus Grant
Bus Grant Acknowledge
Reset
Halt
Bus Error
Cache Disable
Pipe Refill
Microsequencer Status
Mnemonic
FC0–FC2
A0–A31
D0–D31
SIZ0–SIZ1
OCS
ECS
R/W
RMC
AS
DS
DBEN
DSACK0,
DSACK1
STERM
CIIN
CIOUT
CBREQ
CBACK
Function
3-bit function code used to identify the address space of each bus
cycle.
32-bit address bus.
32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus
cycle.
Indicates the number of bytes remaining to be transferred for this
cycle. These signals, together with A0 and A1, define the active
sections of the data bus.
Identical operation to that of ECS except that OCS is asserted only
during the first bus cycle of an operand transfer
Provides an indication that a bus cycle is beginning.
Defines the bus transfer as a controller read or write.
Provides an indicator that the current bus cycle is part of an indivisible
read-modify-write operation.
Indicates that a valid address is on the bus.
Indicates that valid data is to be placed on the data bus by an external
device or has been replaced by the MC68EC030.
Provides an enable signal for external data buffers.
Bus response signals that indicate the requested data transfer
operation has completed. In addition, these two lines indicate the size
of the external bus port on a cycle-by-cycle basis and are used for
asynchronous transfers.
Bus response signal that indicates a port size of 32 bits and that data
may be latched on the next falling clock edge.
Prevents data from being loaded into the MC68EC030 instruction and
data caches.
Reflects the CI bit in ACx registers; indicates that external caches
should ignore these accesses.
Indicates a burst request for the instruction or data cache.
Indicates that the accessed device can operate in burst mode.
IPL0–IPL2
IPEND
AVEC
BR
BG
BGACK
RESET
HALT
BERR
CDIS
REFILL
STATUS
Provides an encoded interrupt level to the controller.
Indicates that an interrupt is pending.
Requests an autovector during an interrupt acknowledge cycle.
Indicates that an external device requires bus mastership.
Indicates that an external device may assume bus mastership.
Indicates that an external device has assumed bus mastership.
System reset.
Indicates that the controller should suspended bus activity.
Indicates that an erroneous bus operation is being attempted.
Dynamically disables the on-chip cache to assist emulator support.
Indicates when the MC68EC030 is beginning to fill pipeline.
Indicates the state of the microsequencer.
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