MCF5307AI66B Datasheet, PDF (289/484 Pages) Motorola, Inc – Integrated Microprocessor User’s Manual

Freescale Semiconductor, Inc.
DMA Controller Module Functional Description
Table 12-4. DSRn Field Descriptions (Continued)
Bits Name
Description
2
REQ Request
0 No request is pending or the channel is currently active. Cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
1
BSY Busy
0 DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1 BSY is set the first time the channel is enabled after a transfer is initiated.
0
DONE Transactions done. Set when all DMA controller transactions complete normally, as determined by
transfer count and error conditions. When BCR reaches zero, DONE is set when the final transfer
completes successfully. DONE can also be used to abort a transfer by resetting the status bits.
When a transfer completes, software must clear DONE before reprogramming the DMA.
0 Writing or reading a 0 has no effect.
1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and can be used as an
interrupt handler to clear the DMA interrupt and error bits.
12.4.6 DMA Interrupt Vector Registers (DIVR0–DIVR3)
The contents of a DMA interrupt vector register (DIVRn), Figure 12-10, are driven onto the
internal bus in response to an interrupt acknowledge cycle.
7
0
Field
Interrupt Vector Bits
Reset
0000_1111
R/W
R/W
Address
MBAR + 0x314, 0x354, 0x394, 0x3D4
Figure 12-10. DMA Interrupt Vector Registers (DIVRn)
12.5 DMA Controller Module Functional Description
In the following discussion, the term ‘DMA request’ implies that DCR[START] or
DCR[EEXT] is set, followed by assertion of DREQ. The START bit is cleared when the
channel begins an internal access.
Before initiating a dual-address access, the DMA module verifies that DCR[SSIZE,DSIZE]
are consistent with the source and destination addresses. If the source and destination are
not the same size, the configuration error bit, DSR[CE], is also set. If misalignment is
detected, no transfer occurs, CE is set, and, depending on the DCR configuration, an
interrupt event is issued. Note that if the auto-align bit, DCR[AA], is set, error checking is
performed on appropriate registers.
A read/write transfer reads bytes from the source address and writes them to the destination
address. The number of bytes is the larger of the sizes specified by SSIZE and DSIZE. See
Section 12.4.4, “DMA Control Registers (DCR0–DCR3).”
Source and destination address registers (SAR and DAR) can be programmed in the DCR
Chapter 12. DMA Controller Module
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