MCF5307AI66B Datasheet, PDF (267/484 Pages) Motorola, Inc – Integrated Microprocessor User’s Manual

Freescale Semiconductor, Inc.
Synchronous Operation
11.4.5 Initialization Sequence
Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller
supports this sequence with the following procedure:
1. SDRAM control signals are reset to idle state. Wait the prescribed period after reset
before any action is taken on the SDRAMs. This is normally around 100 µs.
2. Initialize the DCR, DACR, and DMR in their operational configuration. Do not yet
enable PALL or REF commands.
3. Issue a PALL command to the SDRAMs by setting DCR[IP] and accessing a
SDRAM location. Wait the time (determined by t_RP) before any other execution.
4. Enable refresh (set DACR[RE]) and wait for at least 8 refreshes to occur.
5. Before issuing the MRS command, determine if the DMR mask bits need to be
modified to allow the MRS to execute properly
6. Issue the MRS command by setting DACR[IMRS] and accessing a location in the
SDRAM. Note that mode register settings are driven on the SDRAM address bus, so
care must be taken to change DMR[BAM] if the mode register configuration does
not fall in the address range determined by the address mask bits. After the mode
register is set, DMR mask bits can be restored to their desired configuration.
11.4.5.1 Mode Register Settings
It is possible to configure the operation of SDRAMs, namely their burst operation and CAS
latency, through the SDRAM component’s mode register. CAS latency is a function of the
speed of the SDRAM and the bus clock of the DRAM controller. The DRAM controller
operates at a CAS latency of 1, 2, or 3.
Although the MCF5307 DRAM controller supports bursting operations, it does not use the
bursting features of the SDRAMs. Because the MCF5307 can burst operand sizes of 1, 2,
4, or 16 bytes long, the concept of a fixed burst length in the SDRAMs mode register
becomes problematic. Therefore, the MCF5307 DRAM controller generates the burst
cycles rather than the SDRAM device. Because the MCF5307 generates a new address and
a READ or WRITE command for each transfer within the burst, the SDRAM mode register
should be set either to a burst length of one or to not burst. This allows bursting to be
controlled by the MCF5307 instead.
The SDRAM mode register is written by setting the associated block’s DACR[IMRS].
First, the base address and mask registers must be set to the appropriate configuration to
allow the mode register to be set. Note that improperly set DMR mask bits may prevent
access to the mode register address. Thus, the user should determine the mapping of the
mode register address to the MCF5307 address bits to find out if an access is blocked. If the
DMR setting prohibits mode register access, the DMR should be reconfigured to enable the
access and then set to its necessary configuration after the MRS command executes.
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
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