MCF5307AI66B Datasheet, PDF (25/484 Pages) Motorola, Inc – Integrated Microprocessor User’s Manual

Freescale Semiconductor, Inc.
Table
Number
TABLES
Title
Page
Number
1-1 User-Level Registers................................................................................................... 1-14
1-2 Supervisor-Level Registers......................................................................................... 1-14
2-1 CCR Field Descriptions ............................................................................................. 2-28
2-2 MOVEC Register Map ............................................................................................... 2-29
2-3 Status Field Descriptions ............................................................................................ 2-30
2-4 Integer Data Formats................................................................................................... 2-31
2-5 ColdFire Effective Addressing Modes........................................................................ 2-34
2-6 Notational Conventions .............................................................................................. 2-34
2-7 User-Mode Instruction Set Summary ......................................................................... 2-37
2-8 Supervisor-Mode Instruction Set Summary................................................................ 2-40
2-9 Misaligned Operand References ................................................................................. 2-41
2-10 Move Byte and Word Execution Times...................................................................... 2-42
2-11 Move Long Execution Times...................................................................................... 2-42
2-12 MAC Move Execution Times..................................................................................... 2-43
2-13 One-Operand Instruction Execution Times ................................................................ 2-43
2-14 Two-Operand Instruction Execution Times................................................................ 2-44
2-15 Miscellaneous Instruction Execution Times............................................................... 2-45
2-16 General Branch Instruction Execution Times............................................................. 2-46
2-17 Bcc Instruction Execution Times................................................................................ 2-47
2-18 Exception Vector Assignments................................................................................... 2-48
2-19 Format Field Encoding ............................................................................................... 2-49
2-20 Fault Status Encodings................................................................................................ 2-50
2-21 MCF5307 Exceptions ................................................................................................. 2-50
3-1 MAC Instruction Summary........................................................................................... 3-4
3-2 Two-Operand MAC Instruction Execution Times ....................................................... 3-5
3-3 MAC Move Instruction Execution Times..................................................................... 3-6
4-1 RAMBAR Field Description ........................................................................................ 4-3
4-2 Examples of Typical RAMBAR Settings ..................................................................... 4-6
4-3 Valid and Modified Bit Settings ................................................................................... 4-8
4-4 CACR Field Descriptions ........................................................................................... 4-21
4-5 ACRn Field Descriptions............................................................................................ 4-23
4-6 Cache Line State Transitions ...................................................................................... 4-27
4-7 Cache Line State Transitions (Current State Invalid) ................................................. 4-28
4-8 Cache Line State Transitions (Current State Valid) ................................................... 4-28
4-9 Cache Line State Transitions (Current State Modified) ............................................. 4-29
5-1 Debug Module Signals.................................................................................................. 5-2
Tables
xxv
For More Information On This Product,
Go to: www.freescale.com