MCF5307AI66B Datasheet, PDF (233/484 Pages) Motorola, Inc – Integrated Microprocessor User’s Manual

Freescale Semiconductor, Inc.
Chip-Select Registers
Table 10-9. CSCRn Field Descriptions
Bits Name
Description
3 BSTW Burst write enable. Specifies whether burst writes are used for memory associated with each CSn.
0 Break data larger than the specified port size into individual port-sized, non-burst writes. For
example, a longword write to an 8-bit port takes four byte writes.
1 Enables burst write of data larger than the specified port size, including longword writes to 8 and
16-bit ports, word writes to 8-bit ports and line writes to 8-, 16-, and 32-bit ports.
2–0 — Reserved, should be cleared.
10.4.1.4 Code Example
The code below provides an example of how to initialize the chip-selects. Only chip selects
0, 1, 2, and 3 are programmed here; chip selects 4, 5, 6, and 7 are left invalid. MBARx
defines the base of the module address space.
CSAR0 EQU MBARx+0x080 ;Chip select 0 address register
CSMR0 EQU MBARx+0x084 ;Chip select 0 mask register
CSCR0 EQU MBARx+0x08A ;Chip select 0 control register
CSAR1 EQU MBARx+0x08C ;Chip select 1 address register
CSMR1 EQU MBARx+0x090 ;Chip select 1 mask register
CSCR1 EQU MBARx+0x096 ;Chip select 1 control register
CSAR2 EQU MBARx+0x098 ;Chip select 2 address register
CSMR2 EQU MBARx+0x09C ;Chip select 2 mask register
CSCR2 EQU MBARx+0x0A2 ;Chip select 2 control register
CSAR3 EQU MBARx+0x0A4 ;Chip select 3 address register
CSMR3 EQU MBARx+0x0A8 ;Chip select 3 mask register
CSCR3 EQU MBARx+0x0AE ;Chip select 3 control register
CSAR4 EQU MBARx+0x0B0 ;Chip select 4 address register
CSAR4 EQU MBARx+0x0B4 ;Chip select 4 mask register
CSMR4 EQU MBARx+0x0BA ;Chip select 4 control register
CSAR5 EQU MBARx+0x0BC ;Chip select 5 address register
CSMR5 EQU MBARx+0x0C0 ;Chip select 5 mask register
CSCR5 EQU MBARx+0x0C6 ;Chip select 5 control register
CSAR6 EQU MBARx+0x0C8 ;Chip select 6 address register
CSMR6 EQU MBARx+0x0CC ;Chip select 6 mask register
CSCR6 EQU MBARx+0x0D2 ;Chip select 6 control register
CSAR7 EQU MBARx+0x0D4 ;Chip select 7 address register
CSMR7 EQU MBARx+0x0D8 ;Chip select 7 mask register
CSCR7 EQU MBARx+0x0DE ;Chip select 7 control register
; All other chip selects should be programmed and made valid before global
; chip select is de-activated by validating CS0
; Program Chip Select 3 Registers
move.w #0x0040,D0
;CSAR3 base address 0x00400000
move.w D0,CSAR3
move.w #0x00A0,D0
move.w D0,CSCR3
;CSCR3 = no wait states, AA=0, PS=16-bit, BEM=1,
;BSTR=0, BSTW=0
move.l #0x001F016B,D0 ;Address range from 0x00400000 to 0x005FFFFF
move.l D0,CSMR3
;WP,EM,C/I,SD,UD,V=1; SC,UC=0
; Program Chip Select 2 Registers
move.w #0x0020,D0
;CSAR2 base address 0x00200000 (to 0x003FFFFF)
Chapter 10. Chip-Select Module
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