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M38503MXH Datasheet, PDF (79/86 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER | |||
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MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 34 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = â20 to 85 °C, unless otherwise noted)
Symbol
Parameter
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Reset input âLâ pulse width
External clock input cycle time
External clock input âHâ pulse width
External clock input âLâ pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input âHâ pulse width
CNTR0, CNTR1 input âLâ pulse width
INT0 to INT3 input âHâ pulse width
INT0 to INT3 input âLâ pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input âHâ pulse width (Note)
Serial I/O1 clock input âLâ pulse width (Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input âHâ pulse width
Serial I/O2 clock input âLâ pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is â1â (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is â0â (UART).
Min.
20
125
50
50
200
80
80
80
80
800
370
370
220
100
1000
400
400
200
200
Limits
Typ.
Max.
Unit
XIN cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 35 Timing requirements (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = â20 to 85 °C, unless otherwise noted)
Symbol
Parameter
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Reset input âLâ pulse width
External clock input cycle time
External clock input âHâ pulse width
External clock input âLâ pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input âHâ pulse width
CNTR0, CNTR1 input âLâ pulse width
INT0 to INT3 input âHâ pulse width
INT0 to INT3 input âLâ pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input âHâ pulse width (Note)
Serial I/O1 clock input âLâ pulse width (Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input âHâ pulse width
Serial I/O2 clock input âLâ pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is â1â (clock synchronous).
Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is â0â (UART).
Min.
20
250
100
100
500
230
230
230
230
2000
950
950
400
200
2000
950
950
400
300
Limits
Typ.
Max.
Unit
XIN cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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