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M38503MXH Datasheet, PDF (44/86 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER | |||
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MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Status Register
The status register shows the operating state of the flash memory
and whether erase operations and programs ended successfully or
in error. It can be read in the following ways.
(1) By reading an arbitrary address from the user ROM area after
writing the read status register command (7016)
(2) By reading an arbitrary address from the user ROM area in the
period from when the program starts or erase operation starts to
when the read array command (FF16) is input
Table 11 shows the status register.
Also, the status register can be cleared in the following way.
(1) By writing the clear status register command (5016)
(2) In the deep power down mode
(3) In the power supply off state
After a reset, the status register is set to â8016â.
Each bit in this register is explained below.
Sequencer status (SR7)
After power-on, and after recover from deep power down mode, the
sequencer status is set to â1â(ready).
The sequencer status indicates the operating status of the device.
This status bit is set to â0â (busy) during write or erase operation and
is set to â1â upon completion of these operations.
Erase status (SR5)
The erase status informs the operating status of erase operation to
the CPU. When an erase error occurs, it is set to â1â.
The erase status is reset to â0â when cleared.
Program status (SR4)
The program status informs the operating status of write operation to
the CPU. When a write error occurs, it is set to â1â.
The program status is reset to â0â when cleared.
If â1â is written for any of the SR5 or SR4 bits, the program, erase all
blocks, and block erase commands are not accepted. Before ex-
ecuting these commands, execute the clear status register com-
mand (5016) and clear the status register.
Also, any commands are not correct, both SR5 and SR4 are set to
â1â.
Table 11 Definition of each bit in status register
Each bit of
SRD0 bits
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Status name
Sequencer status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
Definition
â1â
â0â
Ready
Busy
-
-
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
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