M38503MXH Datasheet, PDF (46/86 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of the flash memory version from being read
out or rewritten easily, the device incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check function
for use in standard serial I/O mode.
ROM code protect function
The ROM code protect function is the function inhibit reading out or
modifying the contents of the flash memory version by using the
ROM code protect control address (FFDB16) during parallel I/O
mode. Figure 50 shows the ROM code protect control address
(FFDB16). (This address exists in the user ROM area.)
If one of the pair of ROM code protect bits is set to “0”, ROM code
protect is turned on, so that the contents of the flash memory ver-
sion are protected against readout and modification. ROM code
protect is implemented in two levels. If level 2 is selected, the flash
memory is protected even against readout by a shipment inspection
LSI tester, etc. When an attempt is made to select both level 1 and
level 2, level 2 is selected by default.
If both of the two ROM code protect reset bits are set to “00”, ROM
code protect is turned off, so that the contents of the flash memory
version can be read out or modified. Once ROM code protect is
turned on, the contents of the ROM code protect reset bits cannot
be modified in parallel I/O mode. Use the serial I/O or some other
mode to rewrite the contents of the ROM code protect reset bits.
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol
ROMCP
Address
FFDB16
When reset
FF16
Bit symbol
Reserved bit
Bit name
Function
Always set this bit to “1”
ROMCP2
ROM code protect level
2 set bit (Note 1, 2)
b3 b2
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
ROMCR ^{ROM code protect reset}
bit (Note 3)
ROMCP1 ^{ROM code protect level}
1 set bit (Note 1)
b5 b4
00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
b7 b6
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
Notes 1: When ROM code protect is turned on, the on-chip flash memory is protected against
readout or modification in parallel input/output mode.
2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and
ROM code protect level 2. However, since these bits cannot be changed in parallel
input/output mode, they need to be rewritten in serial input/output mode or some other
mode.
Fig. 50 ROM code protect control address
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