M34512M2 Datasheet, PDF (5/80 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
4512 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MULTIFUNCTION
Pin
P20
P21
P22
Multifunction
SCK
SOUT
SIN
Pin
SCK
SOUT
SIN
Multifunction
P20
P21
P22
Notes 1: Pins except above have just single function.
2: The input of P20–P22 can be used even when SCK, SOUT, SIN are
selected.
DEFINITION OF CLOCK AND CYCLE
q System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the bit 3 of the clock control reg-
ister MR.
Table Selection of system clock
Register MR
MR3
System clock
0
f(XIN)
1
f(XIN)/2
Note: f(XIN)/2 is selected after system is released from reset.
q Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.
q Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
CONNECTIONS OF UNUSED PINS
Pin
XOUT
N.F
D0–D7
Connection
Open (when using an external clock).
Connect to VSS.
Connect to VSS, or set the output latch
to “0” and open.
P20/SCK
Connect to VSS.
P21/SOUT
P22/SIN
INT0
Connect to VSS.
INT1
AIN0–AIN3
P00–P03
P10–P13
Connect to VSS.
Open or connect to VSS (Note)
Open or connect to VSS (Note)
Note: When the P00–P03 and P10–P13 are connected to VSS, turn off their
pull-up transistors (register PU0i=“0”) and also invalidate the key-on
wakeup functions (register K0i=“0”) by software. When these pins are
connected to VSS while the key-on wakeup functions are left valid, the
system fails to return from RAM back-up state. When these pins are
open, turn on their pull-up transistors (register PU0i=“1”) by software,
or set the output latch to “0.”
Be sure to select the key-on wakeup functions and the pull-up func-
tions with every two pins. If only one of the two pins for the key-on
wakeup function is used, turn on their pull-up transistors by software
and also disconnect the other pin. (i = 0, 1, 2, or 3.)
(Note when the output latch is set to “0” and pins are open)
q After system is released from reset, port is in a high-impedance state un-
til it is set the output latch to “0” by software. Accordingly, the voltage
level of pins is undefined and the excess of the supply current may occur
while the port is in a high-impedance state.
q To set the output latch periodically by software is recommended because
value of output latch may change by noise or a program run away
(caused by noise).
(Note when connecting to VSS and VDD)
q Connect the unused pins to VSS and VDD using the thickest wire at the
shortest distance against noise.
PORT FUNCTION
Port
Pin
Port D D0–D7
Port P0 P00–P03
Port P1 P10–P13
Port P2
P20/SCK
P21/SOUT
P22/SIN
Input
Output
I/O
(8)
Output structure
N-channel open-drain
I/O N-channel open-drain
(4)
I/O N-channel open-drain
(4)
Input
(3)
I/O
Control
Control
unit instructions registers
Remark
1
SD, RD
SZD
CLD
4
OP0A
IAP0
PU0, K0
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
4
OP1A
IAP1
PU0, K0
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
3
IAP2
J1
5