M34512M2 Datasheet, PDF (33/80 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
4512 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Table 15 A-D control registers
A-D control register Q1
at reset : 00002
at RAM back-up : state retained
Q13 Not used
Q12
Q11 Analog input pin selection bits
Q10
0
This bit has no function, but read/write is enabled.
1
Q12Q11Q10
Selected pins
0 0 0 AIN0
0 0 1 AIN1
0 1 0 AIN2
0 1 1 AIN3
1 0 0 Not available
1 0 1 Not available
1 1 0 Not available
1 1 1 Not available
A-D control register Q2
at reset : 00002
at RAM back-up : state retained
0
Q23 A-D operation mode selection bit
1
0
Q22 Not used
1
0
Q21 Not used
1
0
Q20 Not used
1
Note: “R” represents read enabled, and “W” represents write enabled.
A-D conversion mode
Comparator mode
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
R/W
R/W
(1) Operating at A-D conversion mode
The A-D conversion mode is set by setting the bit 3 of register Q2 to “0.”
(2) Successive comparison register AD
Register AD stores the A-D conversion result of an analog input in
10-bit digital data format. The contents of the high-order 8 bits of
this register can be stored in register B and register A with the
TABAD instruction. The contents of the low-order 2 bits of this reg-
ister can be stored into the high-order 2 bits of register A with the
TALA instruction. However, do not execute this instruction during A-
D conversion.
When the contents of register AD is n, the logic value of the com-
parison voltage Vref generated from the built-in DA converter can
be obtained with the reference voltage VDD by the following for-
mula:
(4) A-D conversion start instruction (ADST)
A-D conversion starts when the ADST instruction is executed. The
conversion result is automatically stored in the register AD.
(5) A-D control register Q1
Register Q1 is used to select one of analog input pins.
(6) A-D control register Q2
Register Q2 controls the A-D conversion mode. The A-D conver-
sion mode is selected when the bit 3 of register Q2 is “0,” and the
comparator mode is selected when the bit 3 of register Q2 is “1.”
Logic value of comparison voltage Vref
Vref =
VDD
1024
!n
n: The value of register AD (n = 0 to 1023)
(3) A-D conversion completion flag (ADF)
A-D conversion completion flag (ADF) is set to “1” when A-D con-
version completes. The state of ADF flag can be examined with the
skip instruction (SNZAD). Use the interrupt control register V2 to
select the interrupt or the skip instruction.
The ADF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
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