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M34512M2 Datasheet, PDF (34/80 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER | |||
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MITSUBISHI MICROCOMPUTERS
4512 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(7) Operation description
A-D conversion is started with the A-D conversion start instruction
(ADST). The internal operation during A-D conversion is as follows:
 When A-D conversion starts, the register AD is cleared to
â00016.â
 Next, the topmost bit of the register AD is set to â1,â and the
comparison voltage Vref is compared with the analog input volt-
age VIN.
 When the comparison result is Vref < VIN, the topmost bit of the
register AD remains set to â1.â When the comparison result is
Vref > VIN, it is cleared to â0.â
The 4512 Group repeats this operation to the lowermost bit of the
register AD to convert an analog value to a digital value. A-D con-
version stops after 62 machine cycles (46.5 µs when f(XIN) = 4.0
MHz in high-speed mode) from the start, and the conversion result
is stored in the register AD. An A-D interrupt activated condition is
satisfied and the ADF flag is set to â1â as soon as A-D conversion
completes (Figure 27).
Table 16 Change of successive comparison register AD during A-D conversion
At starting conversion
1st comparison
2nd comparison
3rd comparison
Change of successive comparison register AD
-------------
1
0
0 ----- 0
0
0
-------------
-------------
U1
1
0 ----- 0
0
0
-------------
-------------
U1 U2
1
----- 0
0
0
-------------
After 10th comparison
completes
A-D conversion result
-------------
U1 U2 U3 ----- U8 U9 UA
-------------
U1: 1st comparison result
U3: 3rd comparison result
U9: 9th comparison result
U2: 2nd comparison result
U8: 8th comparison result
UA: 10th comparison result
VDD
2
VDD
2
VDD
2
VDD
2
Comparison voltage (Vref) value
VDD
±
4
VDD
VDD
± 4 ±8
±
â
â
â
â
±
VDD
1024
(8) A-D conversion timing chart
Figure 27 shows the A-D conversion timing chart.
ADST instruction
A-D conversion
completion flag (ADF)
DAC operation signal
Fig. 27 A-D conversion timing chart
62 machine cycles
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