M34512M2 Datasheet, PDF (42/80 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PRELIMINARY _{NSocothimcaene:gpTeah.riasmisetnrioct} ^{laimfiintsalasrepescuibfijceacttioton.}
MITSUBISHI MICROCOMPUTERS
4512 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Table 20 Key-on wakeup control register, pull-up control register, and interrupt control register
Key-on wakeup control register K0
Pins P12 and P13 key-on wakeup
K03
control bit
Pins P10 and P11 key-on wakeup
K02
control bit
Pins P02 and P03 key-on wakeup
K01
control bit
Pins P00 and P01 key-on wakeup
K00
control bit
at reset : 00002
at RAM back-up : state retained
R/W
0
Key-on wakeup not used
1
Key-on wakeup used
0
Key-on wakeup not used
1
Key-on wakeup used
0
Key-on wakeup not used
1
Key-on wakeup used
0
Key-on wakeup not used
1
Key-on wakeup used
PU03
PU02
PU01
PU00
Pull-up control register PU0
Pins P12 and P13 pull-up transistor
control bit
Pins P10 and P11 pull-up transistor
control bit
Pins P02 and P03 pull-up transistor
control bit
Pins P00 and P01 pull-up transistor
control bit
at reset : 00002
at RAM back-up : state retained
R/W
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
Interrupt control register I1
I13
Not used
Interrupt valid waveform for INT0 pin/
I12
return level selection bit (Note 2)
I11
INT0 pin edge detection circuit control bit
INT0 pin
I10
timer 1 control enable bit
at reset : 00002
at RAM back-up : state retained
R/W
0
This bit has no function, but read/write is enabled.
1
Falling waveform (“L” level of INT0 pin is recognized with the SNZI0
0
instruction)/“L” level
Rising waveform (“H” level of INT0 pin is recognized with the SNZI0
1
instruction)/“H” level
0
One-sided edge detected
1
Both edges detected
0
Disabled
1
Enabled
Interrupt control register I2
at reset : 00002
at RAM back-up : state retained
R/W
I23
Not used
0
This bit has no function, but read/write is enabled.
1
Interrupt valid waveform for INT1 pin/
I22
return level selection bit (Note 3)
Falling waveform (“L” level of INT1 pin is recognized with the SNZI1
0
instruction)/“L” level
Rising waveform (“H” level of INT1 pin is recognized with the SNZI1
1
instruction)/“H” level
I21
INT1 pin edge detection circuit control bit
0
One-sided edge detected
1
Both edges detected
INT1 pin
I20
timer 3 control enable bit
0
Disabled
1
Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.
3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
42