M37270MF Datasheet, PDF (28/94 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(1) Clamping Circuit and Low-pass Filter
This filter attenuates the noise of the composite video signal input
from the CVIN pin. The CVIN pin to which composite video signal is
input requires a capacitor (0.1 µF) coupling outside. Pull down the
CVIN pin with a resistor of hundreds of kiloohms to 1 M . In addition,
we recommend to install externally a simple low-pass filter using a
resistor and a capacitor at the CVIN pin (refer to Figure 19).
(2) Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal
of the low-pass filter. Figure 21 shows the structure of the sync slice
register.
(3) Synchronizing Signal Separation Circuit
This circuit separates a horizontal synchronizing signal and a vertical
synchronizing signal from the composite sync signal taken out in the
sync slice circuit.
ΠHorizontal synchronizing signal (Hsep)
A one-shot horizontal synchronizing signal Hsep is generated at
the falling edge of the composite sync signal.
 Vertical synchronizing signal (Vsep)
As a Vsep signal generating method, it is possible to select one of
the following 2 methods by using bit 7 of the sync slice register
(address 00E316).
•Method 1 The “L” level width of the composite sync signal is
measured. If this width exceeds a certain time, a Vsep
signal is generated in synchronization with the rising
of the timing signal immediately after this “L” level.
•Method 2 The “L” level width of the composite sync signal is
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync
signal exits or not in the “L” level period of the timing
signal immediately after this “L” level. If a falling exists,
a Vsep signal is generated in synchronization with
the rising of the timing signal (refer to Figure 22).
Figure 22 shows a Vsep generating timing. The timing signal shown
in the figure is generated from the reference clock which the timing
generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 23, when the A level matches the B level, this bit is
“0.” In the case of a mismatch, the bit is “1.”
For the pins RVCO and the HLF, connect a resistor and a capacitor
as shown in Figure 19. Make the length of wiring which is connected
to these pins as short as possible so that a leakage current may not
be generated.
Note: It takes a few tens of milliseconds until the reference clock
becomes stable after the data slicer and the timing signal
generating circuit are started. In this period, various timing
signals, Hsep signals and Vsep signals become unstable. For
this reason, take stabilization time into consideration when
programming.
7
0
0 0 0 0 10 1
Sync slice register
(SSL : address 00E316)
Fix these bits to “00001012”
Vertical synchronizing
signal (Vsep) generating
method selection bit
0 : Method 1
1 : Method 2
Fig. 21. Structure of sync slice register
Composite
sync signal
Timing
signal
Measure “L” period
Vsep signal
A Vsep signal is generated at a rising of the timing signal
immediately after the “L” level width of the composite
sync signal exceeds a certain time.
Fig. 22. Vsep generating timing (method 2)
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