M37270MF Datasheet, PDF (27/94 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Figure 19 shows the structure of the data slicer control registers.
7
0
00
0
Data slicer control register 1
(DSC1: address 00E A16)
7
0
Data slicer control bit
0: Data slicer stopped
1: Data slicer operating
Field to be sliced data selection bit
b2 b1
00
01
10
11
Field of main data
slice line
F2
F1
F1 and F2
F1 and F2
Field for setting
reference voltage
F2
F1
F2
F1
Fix these bits to “0.”
00
Field determination flag
0 : Hsep
Vsep
1 : Hsep
Vsep
Fix this bit to “0.”
0
Data slicer control register 2
(DSC2: address 00E B16)
Timing signal generating circuit
control bit
0: Stopped
1: Operating
Reference clock source selection
bit
0: Video signal
1: HSYNC signal
Test bit: read-only
Fix these bits to “0.”
V-pulse shape determination flag
0: Match
1: Mismatch
Fix this bit to “0.”
Test bit: read-only
Data latch completion flag for caption
7
data in main data slice line
0: Data is not yet latched
1: Data is latched
Definition of fields 1 (F1) and 2 (F2)
F1 : Hsep
VSYNC
Vsep
F2 : Hsep
VSYNC
Vsep
0
Data slicer control register 3
(DSC3: address 021016)
Line selection bit for slice voltage
0: Main data slice line
1: Sub-data slice line
Field to be sliced data selection bit
b2 b1
00
01
10
11
Field of sub-data Field for setting
slice line
reference voltage
F2
F2
F1
F1
F1 and F2
F2
F1 and F2
F1
Setting bit of sub-data slice line
Fig. 20. Structure of data slicer control registers
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