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M37270MF Datasheet, PDF (24/94 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER | |||
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MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(6) Conversion Method
 Set bit 7 of the interrupt interval determination control register (ad-
dress 021216) to â1â to generate an interrupt request at comple-
tion of A-D conversion.
 Set the A-D conversion ⢠INT3 interrupt request bit to â0â (even
when A-D conversion is started, the A-D conversion ⢠INT3 inter-
rupt bit is not set to â0â automatically).
 When using A-D conversion interrupt, enable interrupts by setting
A-D conversion ⢠INT3 interrupt request bit to â1â and setting the
interrupt disable flag to â0.â
 Set the VCC connection selection bit to â1â to connect VCC to the
resistor ladder.
 Select analog input pins by setting the analog input selection bit of
the A-D control register.
 Set the A-D conversion completion bit to â0.â This write operation
starts the A-D conversion. Do not read the A-D conversion regis-
ter during the A-D conversion.
 Verify the completion of the conversion by the state (â1â) of the
A-D conversion completion bit, that (â1â) of A-D conversion ⢠INT3
interrupt bit, or the occurrence of an A-D conversion interrupt.
 Read the A-D conversion register to obtain the conversion results.
Note : When the ladder resistor is disconnect from VCC, set the VCC
connection selection bit to â0â between steps  and Â.
(7) Internal Operation
At the time when the A-D conversion starts, the following operations
are automatically performed.
 The A-D conversion register is set to â0016.â
 The most significant bit of the A-D conversion register becomes
â1, â and the comparison voltage âVrefâ is input to the comparator.
At this point, Vref is compared with the analog input voltage âVIN .â
 Bit 7 is determined by the comparison result as follows.
When Vref < VIN : bit 7 holds â1â
When Vref > VIN : bit 7 becomes â0â
With the above operations, the analog value is converted into a digi-
tal value. The A-D conversion terminates in a maximum 50 machine
cycles (12.5µs at f(XIN) = 8 MHz) after it starts, and the conversion
result is stored in the A-D conversion register.
An A-D conversion interrupt request occurs at the same time of A-D
conversion completion, the A-D conversion ⢠INT3 interrupt request
bit becomes â1.â The A-D conversion completion bit also becomes
â1.â
Table 2. Expression for Vref and VREF
A-D conversion register contents ânâ
(decimal notation)
0
Vref (V)
0
1 to 255
VREF ! (n â 0.5)
256
Note: VREF indicates the voltage of internal VCC.
A-D conversion start
Contents of A-D conversion register
00000 00 0
Reference voltage (Vref) [V]
0
1st comparison start
2nd comparison start
3rd comparison start
10000 00 0
1 1000 00 0
12 100 00 0
8th comparison start
12 3 45 6 7 1
VR EF â VR EF
2
512
VR EF ± VR EF â VR EF
2
4
512
VR EF ± VR EF ± VR EF â VR EF
2
4
8
512
VR EF ± VR EF ± VR EF ± .....
2
4
8
....... ± VR EF â VR EF
256 512
A-D conversion completion
(8th comparison completion)
12 3 45 6 78
Digital value corresponding to
analog input voltage.
m : Value determined by mth (m = 1 to 8) result
Fig. 17. Changes in A-D conversion register and comparison voltage during A-D conversion
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