SMJ44400 Datasheet, PDF (7/21 Pages) Austin Semiconductor – 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY

DRAM
SMJ44400
TIMING REQUIREMENTS (continued)
SYM
PARAMETER
-8
-10
-12
MIN MAX MIN MAX MIN MAX
UNIT
t_RAD Delay time, RAS\ low to column address¹
15 40 20 50 20 65
ns
t_RAL Delay time, column addresss to RAS\ High
40
50
55
ns
t_CAL Delay time, column addresss to CAS\ High
40
50
55
ns
t_RCD Delay time, RAS\ low to CAS\ low¹
20 60 25 75 25 90
ns
t_RPC Delay time, RAS\ High to CAS\ low
0
0
0
ns
t_RSH Delay time, CAS\ low to RAS\ High
20
25
30
ns
t_RWD
Delay time, RAS\ low to W\ low
(read-write operation only)
110
135
160
ns
t_CLZ CAS\ to output in low Z²
0
0
0
ns
t_OED OE\ to data delay
20
25
30
ns
t_REF Refresh time interval
16
16
16
ms
t_T
Tranistion time³
NOTES:
1. Maximum value specified only to assure access time.
2. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access times as the outputs are driven when
CAS\ and OE\ are low.
3. Transition times (rise and fall) for RAS\ and CAS\ are to be a minimum of 3ns and a maximum of 50ns.
PARAMETER MEASUREMENT INFORMATION
Figure 1. Load Circuit for Timing Parameters
1.31V
Output Under Test
CL = 100 pF¹
R_L = 218Ω
Output Under Test
CL = 100 pF¹
5V
R₁ = 828Ω
R₂ = 295Ω
(a) LOAD CIRCUIT
NOTES:
1. C_L includes probe and fixture capacitance.
(b) ALTERNATE LOAD CIRCUIT
SMJ44400
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
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