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SMJ44400 Datasheet, PDF (6/21 Pages) Austin Semiconductor – 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY
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DRAM
SMJ44400
TIMING REQUIREMENTS (-55oC<TA<125oC or -40oC to +85oC; Vcc = 5V +10%)
SYM
tRC
tRWC
tPC
tPRWC
tRASP
tRAS
tCAS
tCP
tRP
tWP
tASC
tASR
tDS
tRCS
tCWL
tRWL
tWCS
PARAMETER
Cycle time, random read or write1
Cycle time, read-write
Cycle time, page-mode read or write2
Cycle time, page-mode read-write
Pulse duration, page mode, RAS\ low3
Pulse duration, nonpage mode, RAS\ low3
Pulse duration, CAS\ low4
Pulse duration, CAS\ High
Pulse duration, RAS\ High (precharge)
Pulse duration, write
Setup time, column address before CAS\ low
Setup time, row address before RAS\ low
Setup time, data5
Setup time, read before CAS\ low
Setup time, W\ low before CAS\ high
Setup time, W\ low before RAS\ high
Setup time, W\ low before CAS\ low
(early-write operation only)
-8
MIN MAX
150
-10
MIN MAX
180
-12
MIN MAX
210
205
245
285
50
60
65
100
120
135
80 100000 100 100000 120 100000
80 10000 100 10000 120 10000
20 10000 25 10000 30 10000
10
10
15
60
70
80
15
20
25
0
0
0
0
0
0
0
0
0
0
0
0
20
25
30
20
25
30
0
0
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWSR Setup time, W\ High (CBR refresh only)
10
10
10
ns
tCAH Hold time, column address after CAS\ low
15
20
20
ns
tDHR Hold time, data after RAS\ low
60
75
90
ns
tDH Hold time, data5
15
20
25
ns
tAR Hold time, column address after CAS\ low4
60
75
90
ns
tRAH Hold time, row address after RAS\ low
10
15
15
ns
tRCH Hold time, read after CAS\ High6
0
0
0
ns
tRRH Hold time, read after RAS\ High6
0
0
0
ns
tWCH
Hold time, write after CAS\ low
(early-write operation only)
15
20
25
ns
tWCR Hold time, write after RAS\ low4
60
75
90
ns
tWHR Hold time, W\ High (CBR refresh only)
10
10
10
ns
tOEH Hold time, OE\ command
20
25
30
ns
tROH Hold time, RAS\ referenced to OE\
20
25
30
ns
tAWD
Delay time, column address to W\ low
(read-write operation only)
70
80
90
ns
tCHR
Delay time, RAS\ low to CAS\ High
(CBR refresh only)
20
20
25
ns
tCRP Delay time, CAS\ High to RAS\ low
0
0
0
ns
tCSH Delay time, RAS\ low to CAS\ High
80
100
120
ns
tCSR
Delay time, CAS\ low to RAS\ low
(CBR refresh only)
10
10
10
ns
tCWD
Delay time, CAS\ low to W\ low
(read-write operation only)
50
60
70
ns
NOTES:
1. All cycle times assume tT = 5ns.
2. To assure tPC min, tASC should be > tCP.
3. In a read-write cycle, tRWD and tRWL must be observed.
4. In a read-write cycle, tCWD and tCWL must be observed.
5. Referenced to the later of CAS\ or W\ in write operations.
6. Either tRRH or tRCH must be satisfied for a read cycle.
SMJ44400
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
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